From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754667AbbJGO4q (ORCPT ); Wed, 7 Oct 2015 10:56:46 -0400 Received: from gloria.sntech.de ([95.129.55.99]:57448 "EHLO gloria.sntech.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751864AbbJGO4p convert rfc822-to-8bit (ORCPT ); Wed, 7 Oct 2015 10:56:45 -0400 From: Heiko Stuebner To: Xing Zheng Cc: linux-rockchip@lists.infradead.org, Michael Turquette , Stephen Boyd , linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v2 3/9] clk: rockchip: add clock controller for rk3036 Date: Wed, 07 Oct 2015 12:24:32 +0200 Message-ID: <2653032.av3sFfN860@phil> User-Agent: KMail/4.14.10 (Linux/4.1.0-1-amd64; KDE/4.14.10; x86_64; ; ) In-Reply-To: <56036EAE.9040201@rock-chips.com> References: <1442478540-15068-1-git-send-email-zhengxing@rock-chips.com> <5603683F.4020302@rock-chips.com> <56036EAE.9040201@rock-chips.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8BIT Content-Type: text/plain; charset="utf-8" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, Am Donnerstag, 24. September 2015, 11:31:58 schrieb Xing Zheng: > On 2015年09月24日 11:04, Xing Zheng wrote: > >>> #define RK3066_PLL_RATE(_rate, _nr, _nf, _no) \ > >>> > >>> @@ -95,12 +106,31 @@ enum rockchip_pll_type { > >>> > >>> .nb = _nb, \ > >>> > >>> } > >>> > >>> +#define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \ > >>> + _postdiv2, _dsmpd, _frac) \ > >>> +{ \ > >>> + .rate = _rate##U, \ > >>> + .fbdiv = _fbdiv, \ > >>> + .postdiv1 = _postdiv1, \ > >>> + .refdiv = _refdiv, \ > >>> + .postdiv2 = _postdiv2, \ > >>> + .dsmpd = _dsmpd, \ > >>> + .frac = _frac, \ > >>> +} > >>> + > >>> > >>> struct rockchip_pll_rate_table { > >>> > >>> unsigned long rate; > >>> unsigned int nr; > >>> unsigned int nf; > >>> unsigned int no; > >>> unsigned int nb; > >>> > >>> + /* for RK3036 */ > >>> + unsigned int fbdiv; > >>> + unsigned int postdiv1; > >>> + unsigned int refdiv; > >>> + unsigned int postdiv2; > >>> + unsigned int dsmpd; > >>> + unsigned int frac; > >> > >> same for these 2 ... should be part of the pll addition itself > >> > > }; > > > > Done. > > Sorry, I have one question: > The "struct rockchip_pll_rate_table" is called in "rockchip/clk-pll.c" > on many functions, I think I could add a struct like: > struct rk3036_pll_rate_table { > unsigned int fbdiv; > unsigned int postdiv1; > unsigned int refdiv; > unsigned int postdiv2; > unsigned int dsmpd; > unsigned int frac; > }; > but, it will add many redundancy codes in "rockchip/clk-pll.c" just for > call "struct rk3036_pll_rate_table". One possible solution may be to cast to void* in the general functions, so have sturct rk3066_pll_rate_table, rk3036_pll_rate_table, have rockchip_clk_register_pll and friends handle it as void* and then only have the rockchip_rk3066_pll_* functions as well as the clk-rkxxxx.c use them as their actual type, as they know which they need. Heiko