Re: [RFC} arm architecture board/feature deprecation timeline

[jeremy@jeremypeper.com]

On Monday, August 19, 2024 9:23:16 AM CDT Andrew Lunn wrote:
> On Mon, Aug 19, 2024 at 04:12:10PM +0200, Arnd Bergmann wrote:
> > Two small additions:
> > 
> > On Mon, Aug 19, 2024, at 11:17, Arnd Bergmann wrote:
> > > On Thu, Aug 15, 2024, at 21:53, jeremy@jeremypeper.com wrote:
> > > I expect that the terastation pro2 is going to be fairly easy to
> > > convert to DT as there is already support for similar Orion5x
> > > machines. In this case I would just remove all the Orion5x board
> > > files and you can add a dts file later on. The bit I'm unsure
> > > about here is legacy PCI support. I see that the board file enables
> > > both PCI and PCIe, but I don't know if both are actually used,
> > > or if everything is on PCIe.
> > > 
> > > I have some old patches for separating orion legacy PCI from
> > > PCIe support, as only the latter has a modern driver (shared
> > > with kirkwood and armadaxp). If you can confirm that the machine
> > > actually uses PCI, I can dig those out from my backups.
> > 
> > I did find this myself later, the machine does use an on-board
> > PCI connected SATA controller, which is obviously required to
> > make the machine useful.
> > 
> > Doing a PCI host bridge driver with DT support correctly is
> > a lot of work, especially if there is only a single machine
> > using it. Since this uses the same drivers/ata/sata-mv.c
> > driver as the other orion/kirkwood machines, I wonder if we
> > can just pretend that this is a platform device and skip
> > all of the PCI probing. I think this only needs a few
> > small changes to the sata-mv.c driver, but it does require
> > that the PCI bus is left in a known state by the boot loader.
> 
> It is a long time since i looked at Orion, so i could be wrong....
> 
> As far as i remember, it has a PCI controller and a PCIe
> controller. They are slightly different. The PCIe part is i think
> simpler to support, it follows the standards better. I _think_ the PCI
> controller uses a GPIO for interrupt support, which causes a mess.
> 
> If only PCIe is needed, it should not be too hard to make work. I
> would try to avoid the PCI controller is possible.
> 
>       Andrew

Looking at the ts2pro I think it's PCI rather than PCIe but I'm not certain:

0001:01:07.0 SCSI storage controller: Marvell Technology Group Ltd. 88SX6042 
PCI-X 4-Port SATA-II (rev 02)
        Subsystem: Marvell Technology Group Ltd. 88SX6042 PCI-X 4-Port SATA-II
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr+ 
Stepping- SERR+ FastB2B+ DisINTx-
        Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- 
<TAbort- <MAbort- >SERR- <PERR- INTx-
        Latency: 128, Cache Line Size: 32 bytes
        Interrupt: pin A routed to IRQ 44
        Region 0: Memory at e8000000 (64-bit, non-prefetchable) [size=1M]
        Region 2: I/O ports at 10000 [size=256]
        Capabilities: [40] Power Management version 2
                Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA 
PME(D0-,D1-,D2-,D3hot-,D3cold-)
                Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
        Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+
                Address: 0000000000000000  Data: 0000
        Capabilities: [60] PCI-X non-bridge device
                Command: DPERE- ERO- RBC=512 OST=4
                Status: Dev=01:07.0 64bit+ 133MHz+ SCD- USC- DC=simple 
DMMRBC=512 DMOST=4 DMCRS=8 RSCEM- 266MHz- 533MHz-
        Kernel driver in use: sata_mv

root@ts2pro:~# dmesg | grep -i pcie
root@ts2pro:~# dmesg | grep -i pci | head
[   25.598898] PCI host bridge to bus 0000:00
[   25.598924] pci_bus 0000:00: root bus resource [mem 0xe0000000-0xe7ffffff]
[   25.598963] pci_bus 0000:00: root bus resource [io  0x1000-0xffff]
[   25.598993] pci_bus 0000:00: No busn resource found for root bus, will use 
[bus 00-ff]
[   25.599019] pci_bus 0000:00: scanning bus
[   25.599082] pci 0000:00:00.0: [11ab:5281] type 00 class 0x058000
[   25.599127] pci 0000:00:00.0: reg 0x10: [mem 0xf1000000-0xf10fffff 64bit 
pref]
[   25.599166] pci 0000:00:00.0: reg 0x18: [mem 0x00000000-0x07ffffff]
[   25.599687] pci_bus 0000:00: fixups for bus
[   25.599711] PCI: bus0: Fast back to back transfers disabled