Re: [PATCH v5 00/10] Add clock and reset support for Mobileye EyeQ7H

["Benoît Monin" <benoit.monin@bootlin.com>]

On Tuesday, 24 March 2026 at 01:38:07 CET, Stephen Boyd wrote:
> Quoting Benoît Monin (2026-03-17 06:33:02)
> > This patchset brings the support of the Other Logic Blocks (OLB)
> > found in the first Mobileye SoC based on the RISC-V architecture, the
> > EyeQ7H. Despite the change from MIPS to RISC-V, the Other Logic Blocks
> > provide similar clock and reset functions to the controllers of the
> > chip. This series introduces the device tree bindings of the SoC and
> > the necessary changes to the clock and reset eyeq drivers.
> >
> [...]
> > 
> > This series depends on the EyeQ6Lplus support patchset posted
> > previously[1], which in turn depends on Théo's series[2]. In particular,
> > the changes made to the clk-eyeq driver in this patchset depend on the
> > changes done in these two series.
> 
> Is it a build time dependency or a run time dependency? Are you
> expecting me to apply all three series to the clk tree?
> 
It is a build dependency for the changes to the clk-eyeq driver. I am
trying to figure out the best merge strategy. I propose to split the
patches between the mips tree and the clock tree. The changes to the
clk-eyeq driver and the auxiliary pinctrl-eyeq5 and reset-eyeq drivers
could go through the clk tree. In detail, the following patches can
be applied in order to avoid merge conflicts and the series is fully
bisectable:

All the patches from Théo's series[1]:
        [PATCH v7 1/3] clk: eyeq: use the auxiliary device creation helper
        [PATCH v7 2/3] clk: eyeq: add EyeQ5 children auxiliary device for generic PHYs
        [PATCH v7 3/3] reset: eyeq: drop device_set_of_node_from_dev() done by parent

The following patches from the eyeq6lplus series[2]:
        [PATCH v4 02/13] dt-bindings: soc: mobileye: Add EyeQ6Lplus OLB
        [PATCH v4 04/13] reset: eyeq: Add Mobileye EyeQ6Lplus OLB
        [PATCH v4 05/13] pinctrl: eyeq5: Use match data
        [PATCH v4 06/13] pinctrl: eyeq5: Add Mobileye EyeQ6Lplus OLB
        [PATCH v4 07/13] clk: eyeq: Skip post-divisor when computing PLL frequency
        [PATCH v4 08/13] clk: eyeq: Adjust PLL accuracy computation
        [PATCH v4 09/13] clk: eyeq: Add Mobileye EyeQ6Lplus OLB

And the patches from this series:
        [PATCH v5 01/10] dt-bindings: soc: mobileye: Add EyeQ7H OLB
        [PATCH v5 02/10] reset: eyeq: Add EyeQ7H compatibles
        [PATCH v5 03/10] clk: fixed-factor: Rework initialization with parent clocks
        [PATCH v5 04/10] clk: fixed-factor: Export __clk_hw_register_fixed_factor()
        [PATCH v5 05/10] clk: eyeq: Prefix the PLL registers with the PLL type
        [PATCH v5 06/10] clk: eyeq: Introduce a generic clock type
        [PATCH v5 07/10] clk: eyeq: Convert clocks declaration to eqc_clock
        [PATCH v5 08/10] clk: eyeq: Drop PLL, dividers, and fixed factors structs
        [PATCH v5 09/10] clk: eyeq: Add EyeQ7H compatibles

The last patch to the MAINTAINERS file can be left aside for now, I can
include it in the series introducing the EyeQ7H SoC (not yet posted).


[1]: https://lore.kernel.org/lkml/20260225-macb-phy-v7-0-665bd8619d51@bootlin.com/ 
[2]: https://lore.kernel.org/all/20260316-eyeq6lplus-v4-0-bf44dfc7a261@bootlin.com/


Best regards,
-- 
Benoît Monin, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com