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[178.79.73.218]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-63a5c133f58sm9091983a12.30.2025.10.13.08.43.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Oct 2025 08:43:42 -0700 (PDT) From: Jernej =?UTF-8?B?xaBrcmFiZWM=?= To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Samuel Holland , Richard Genoud Cc: Uwe =?UTF-8?B?S2xlaW5lLUvDtm5pZw==?= , Wentao Liang , Johan Hovold , Maxime Ripard , Thomas Petazzoni , linux-mtd@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Richard Genoud Subject: Re: [PATCH v2 15/15] arm64: dts: allwinner: h616: add NAND controller Date: Mon, 13 Oct 2025 17:43:39 +0200 Message-ID: <2800174.mvXUDI8C0e@jernej-laptop> In-Reply-To: <20251013152645.1119308-16-richard.genoud@bootlin.com> References: <20251013152645.1119308-1-richard.genoud@bootlin.com> <20251013152645.1119308-16-richard.genoud@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Dne ponedeljek, 13. oktober 2025 ob 17:26:45 Srednjeevropski poletni =C4=8D= as je Richard Genoud napisal(a): > The H616 has a NAND controller quite similar to the A10/A23 ones, but > with some register differences, more clocks (for ECC and MBUS), more ECC > strengths, so this requires a new compatible string. >=20 > Add the NAND controller node and pins in the device tree. >=20 > Signed-off-by: Richard Genoud > --- > .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 51 +++++++++++++++++++ > 1 file changed, 51 insertions(+) >=20 > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/= boot/dts/allwinner/sun50i-h616.dtsi > index ceedae9e399b..bb53c6c63836 100644 > --- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi > +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi > @@ -304,6 +304,42 @@ mmc2_pins: mmc2-pins { > bias-pull-up; > }; > =20 > + /omit-if-no-ref/ > + nand_pins: nand-pins { > + pins =3D "PC0", "PC1", "PC2", "PC5", "PC8", "PC9", > + "PC10", "PC11", "PC12", "PC13", "PC14", > + "PC15", "PC16"; > + function =3D "nand0"; > + }; > + > + /omit-if-no-ref/ > + nand_cs0_pin: nand-cs0-pin { > + pins =3D "PC4"; > + function =3D "nand0"; > + bias-pull-up; > + }; > + > + /omit-if-no-ref/ > + nand_cs1_pin: nand-cs1-pin { > + pins =3D "PC3"; > + function =3D "nand0"; > + bias-pull-up; > + }; > + > + /omit-if-no-ref/ > + nand_rb0_pin: nand-rb0-pin { > + pins =3D "PC6"; > + function =3D "nand0"; > + bias-pull-up; > + }; > + > + /omit-if-no-ref/ > + nand_rb1_pin: nand-rb1-pin { > + pins =3D "PC7"; > + function =3D "nand0"; > + bias-pull-up; > + }; > + > /omit-if-no-ref/ > spi0_pins: spi0-pins { > pins =3D "PC0", "PC2", "PC4"; > @@ -377,6 +413,21 @@ iommu: iommu@30f0000 { > #iommu-cells =3D <1>; > }; > =20 > + nfc: nand-controller@4011000 { > + compatible =3D "allwinner,sun50i-h616-nand-controller"; > + reg =3D <0x04011000 0x1000>; > + interrupts =3D ; > + clocks =3D <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND0>, > + <&ccu CLK_NAND1>, <&ccu CLK_MBUS_NAND>; > + clock-names =3D "ahb", "mod", "ecc", "mbus"; > + resets =3D <&ccu RST_BUS_NAND>; > + reset-names =3D "ahb"; > + dmas =3D <&dma 10>; > + dma-names =3D "rxtx"; > + #address-cells =3D <1>; > + #size-cells =3D <0>; > + }; Sorry, forgot to mention. This should be marked as disabled, as most of the boards don't have NAND connected. Best regards, Jernej > + > mmc0: mmc@4020000 { > compatible =3D "allwinner,sun50i-h616-mmc", > "allwinner,sun50i-a100-mmc"; >=20