* [PATCH] drm/msm: adreno: a6xx: enable GMU bandwidth voting for x1e80100 GPU
@ 2025-07-21 12:35 Neil Armstrong
2025-07-22 11:49 ` Dmitry Baryshkov
2025-07-24 14:35 ` Akhil P Oommen
0 siblings, 2 replies; 5+ messages in thread
From: Neil Armstrong @ 2025-07-21 12:35 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Konrad Dybcio, Dmitry Baryshkov,
Abhinav Kumar, Jessica Zhang, Marijn Suijten, David Airlie,
Simona Vetter
Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel, Neil Armstrong
The Adreno GPU Management Unit (GMU) can also scale DDR Bandwidth along
the Frequency and Power Domain level, but by default we leave the
OPP core scale the interconnect ddr path.
Declare the Bus Control Modules (BCMs) and the corresponding parameters
in the GPU info struct to allow the GMU to vote for the bandwidth.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
index 00e1afd46b81546eec03e22cda9e9a604f6f3b60..b313505e665ba50e46f2c2b7c34925b929a94c31 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
@@ -1440,6 +1440,17 @@ static const struct adreno_info a7xx_gpus[] = {
.pwrup_reglist = &a7xx_pwrup_reglist,
.gmu_chipid = 0x7050001,
.gmu_cgc_mode = 0x00020202,
+ .bcms = (const struct a6xx_bcm[]) {
+ { .name = "SH0", .buswidth = 16 },
+ { .name = "MC0", .buswidth = 4 },
+ {
+ .name = "ACV",
+ .fixed = true,
+ .perfmode = BIT(2),
+ .perfmode_bw = 10687500,
+ },
+ { /* sentinel */ },
+ },
},
.preempt_record_size = 4192 * SZ_1K,
.speedbins = ADRENO_SPEEDBINS(
---
base-commit: 97987520025658f30bb787a99ffbd9bbff9ffc9d
change-id: 20250721-topic-x1e80100-gpu-bwvote-9fc4690fe5e3
Best regards,
--
Neil Armstrong <neil.armstrong@linaro.org>
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH] drm/msm: adreno: a6xx: enable GMU bandwidth voting for x1e80100 GPU
2025-07-21 12:35 [PATCH] drm/msm: adreno: a6xx: enable GMU bandwidth voting for x1e80100 GPU Neil Armstrong
@ 2025-07-22 11:49 ` Dmitry Baryshkov
2025-07-24 14:35 ` Akhil P Oommen
1 sibling, 0 replies; 5+ messages in thread
From: Dmitry Baryshkov @ 2025-07-22 11:49 UTC (permalink / raw)
To: Neil Armstrong
Cc: Rob Clark, Sean Paul, Konrad Dybcio, Dmitry Baryshkov,
Abhinav Kumar, Jessica Zhang, Marijn Suijten, David Airlie,
Simona Vetter, linux-arm-msm, dri-devel, freedreno, linux-kernel
On Mon, Jul 21, 2025 at 02:35:04PM +0200, Neil Armstrong wrote:
> The Adreno GPU Management Unit (GMU) can also scale DDR Bandwidth along
> the Frequency and Power Domain level, but by default we leave the
> OPP core scale the interconnect ddr path.
>
> Declare the Bus Control Modules (BCMs) and the corresponding parameters
> in the GPU info struct to allow the GMU to vote for the bandwidth.
>
> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
> ---
> drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] drm/msm: adreno: a6xx: enable GMU bandwidth voting for x1e80100 GPU
2025-07-21 12:35 [PATCH] drm/msm: adreno: a6xx: enable GMU bandwidth voting for x1e80100 GPU Neil Armstrong
2025-07-22 11:49 ` Dmitry Baryshkov
@ 2025-07-24 14:35 ` Akhil P Oommen
2025-07-24 14:44 ` Neil Armstrong
1 sibling, 1 reply; 5+ messages in thread
From: Akhil P Oommen @ 2025-07-24 14:35 UTC (permalink / raw)
To: Neil Armstrong, Rob Clark, Sean Paul, Konrad Dybcio,
Dmitry Baryshkov, Abhinav Kumar, Jessica Zhang, Marijn Suijten,
David Airlie, Simona Vetter
Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel
On 7/21/2025 6:05 PM, Neil Armstrong wrote:
> The Adreno GPU Management Unit (GMU) can also scale DDR Bandwidth along
> the Frequency and Power Domain level, but by default we leave the
> OPP core scale the interconnect ddr path.
>
> Declare the Bus Control Modules (BCMs) and the corresponding parameters
> in the GPU info struct to allow the GMU to vote for the bandwidth.
>
> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
> ---
> drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> index 00e1afd46b81546eec03e22cda9e9a604f6f3b60..b313505e665ba50e46f2c2b7c34925b929a94c31 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> @@ -1440,6 +1440,17 @@ static const struct adreno_info a7xx_gpus[] = {
> .pwrup_reglist = &a7xx_pwrup_reglist,
> .gmu_chipid = 0x7050001,
> .gmu_cgc_mode = 0x00020202,
> + .bcms = (const struct a6xx_bcm[]) {
> + { .name = "SH0", .buswidth = 16 },
> + { .name = "MC0", .buswidth = 4 },
> + {
> + .name = "ACV",
> + .fixed = true,
> + .perfmode = BIT(2),
> + .perfmode_bw = 10687500,
This configurations should be similar to X1-45.
-Akhil
> + },
> + { /* sentinel */ },
> + },
> },
> .preempt_record_size = 4192 * SZ_1K,
> .speedbins = ADRENO_SPEEDBINS(
>
> ---
> base-commit: 97987520025658f30bb787a99ffbd9bbff9ffc9d
> change-id: 20250721-topic-x1e80100-gpu-bwvote-9fc4690fe5e3
>
> Best regards,
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] drm/msm: adreno: a6xx: enable GMU bandwidth voting for x1e80100 GPU
2025-07-24 14:35 ` Akhil P Oommen
@ 2025-07-24 14:44 ` Neil Armstrong
2025-07-24 16:45 ` Akhil P Oommen
0 siblings, 1 reply; 5+ messages in thread
From: Neil Armstrong @ 2025-07-24 14:44 UTC (permalink / raw)
To: Akhil P Oommen, Rob Clark, Sean Paul, Konrad Dybcio,
Dmitry Baryshkov, Abhinav Kumar, Jessica Zhang, Marijn Suijten,
David Airlie, Simona Vetter
Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel
On 24/07/2025 16:35, Akhil P Oommen wrote:
> On 7/21/2025 6:05 PM, Neil Armstrong wrote:
>> The Adreno GPU Management Unit (GMU) can also scale DDR Bandwidth along
>> the Frequency and Power Domain level, but by default we leave the
>> OPP core scale the interconnect ddr path.
>>
>> Declare the Bus Control Modules (BCMs) and the corresponding parameters
>> in the GPU info struct to allow the GMU to vote for the bandwidth.
>>
>> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
>> ---
>> drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 11 +++++++++++
>> 1 file changed, 11 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
>> index 00e1afd46b81546eec03e22cda9e9a604f6f3b60..b313505e665ba50e46f2c2b7c34925b929a94c31 100644
>> --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
>> @@ -1440,6 +1440,17 @@ static const struct adreno_info a7xx_gpus[] = {
>> .pwrup_reglist = &a7xx_pwrup_reglist,
>> .gmu_chipid = 0x7050001,
>> .gmu_cgc_mode = 0x00020202,
>> + .bcms = (const struct a6xx_bcm[]) {
>> + { .name = "SH0", .buswidth = 16 },
>> + { .name = "MC0", .buswidth = 4 },
>> + {
>> + .name = "ACV",
>> + .fixed = true,
>> + .perfmode = BIT(2),
>> + .perfmode_bw = 10687500,
>
> This configurations should be similar to X1-45.
Including the perfmode bit ?
+ .perfmode = BIT(3),
+ .perfmode_bw = 16500000,
Neil
>
> -Akhil
>
>> + },
>> + { /* sentinel */ },
>> + },
>> },
>> .preempt_record_size = 4192 * SZ_1K,
>> .speedbins = ADRENO_SPEEDBINS(
>>
>> ---
>> base-commit: 97987520025658f30bb787a99ffbd9bbff9ffc9d
>> change-id: 20250721-topic-x1e80100-gpu-bwvote-9fc4690fe5e3
>>
>> Best regards,
>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] drm/msm: adreno: a6xx: enable GMU bandwidth voting for x1e80100 GPU
2025-07-24 14:44 ` Neil Armstrong
@ 2025-07-24 16:45 ` Akhil P Oommen
0 siblings, 0 replies; 5+ messages in thread
From: Akhil P Oommen @ 2025-07-24 16:45 UTC (permalink / raw)
To: Neil Armstrong, Rob Clark, Sean Paul, Konrad Dybcio,
Dmitry Baryshkov, Abhinav Kumar, Jessica Zhang, Marijn Suijten,
David Airlie, Simona Vetter
Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel
On 7/24/2025 8:14 PM, Neil Armstrong wrote:
> On 24/07/2025 16:35, Akhil P Oommen wrote:
>> On 7/21/2025 6:05 PM, Neil Armstrong wrote:
>>> The Adreno GPU Management Unit (GMU) can also scale DDR Bandwidth along
>>> the Frequency and Power Domain level, but by default we leave the
>>> OPP core scale the interconnect ddr path.
>>>
>>> Declare the Bus Control Modules (BCMs) and the corresponding parameters
>>> in the GPU info struct to allow the GMU to vote for the bandwidth.
>>>
>>> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
>>> ---
>>> drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 11 +++++++++++
>>> 1 file changed, 11 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/
>>> drm/msm/adreno/a6xx_catalog.c
>>> index
>>> 00e1afd46b81546eec03e22cda9e9a604f6f3b60..b313505e665ba50e46f2c2b7c34925b929a94c31 100644
>>> --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
>>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
>>> @@ -1440,6 +1440,17 @@ static const struct adreno_info a7xx_gpus[] = {
>>> .pwrup_reglist = &a7xx_pwrup_reglist,
>>> .gmu_chipid = 0x7050001,
>>> .gmu_cgc_mode = 0x00020202,
>>> + .bcms = (const struct a6xx_bcm[]) {
>>> + { .name = "SH0", .buswidth = 16 },
>>> + { .name = "MC0", .buswidth = 4 },
>>> + {
>>> + .name = "ACV",
>>> + .fixed = true,
>>> + .perfmode = BIT(2),
>>> + .perfmode_bw = 10687500,
>>
>> This configurations should be similar to X1-45.
>
> Including the perfmode bit ?
>
> + .perfmode = BIT(3),
> + .perfmode_bw = 16500000,
>
Yes, both.
-Akhil
>
> Neil
>
>>
>> -Akhil
>>
>>> + },
>>> + { /* sentinel */ },
>>> + },
>>> },
>>> .preempt_record_size = 4192 * SZ_1K,
>>> .speedbins = ADRENO_SPEEDBINS(
>>>
>>> ---
>>> base-commit: 97987520025658f30bb787a99ffbd9bbff9ffc9d
>>> change-id: 20250721-topic-x1e80100-gpu-bwvote-9fc4690fe5e3
>>>
>>> Best regards,
>>
>
^ permalink raw reply [flat|nested] 5+ messages in thread
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2025-07-21 12:35 [PATCH] drm/msm: adreno: a6xx: enable GMU bandwidth voting for x1e80100 GPU Neil Armstrong
2025-07-22 11:49 ` Dmitry Baryshkov
2025-07-24 14:35 ` Akhil P Oommen
2025-07-24 14:44 ` Neil Armstrong
2025-07-24 16:45 ` Akhil P Oommen
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