From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0BF41C32792 for ; Wed, 24 Aug 2022 17:42:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240049AbiHXRmG (ORCPT ); Wed, 24 Aug 2022 13:42:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48154 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238822AbiHXRmD (ORCPT ); Wed, 24 Aug 2022 13:42:03 -0400 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 57FFD7E82D; Wed, 24 Aug 2022 10:42:00 -0700 (PDT) Received: from ip5b412258.dynamic.kabel-deutschland.de ([91.65.34.88] helo=diego.localnet) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1oQuNv-0004hr-Rm; Wed, 24 Aug 2022 19:41:47 +0200 From: Heiko =?ISO-8859-1?Q?St=FCbner?= To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt , Paul Walmsley , Albert Ou , linux-riscv@lists.infradead.org Cc: Daniel Lezcano , Anup Patel , Conor Dooley , Guo Ren , Sagar Kadam , Jessica Clarke , Andrew Jones , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, qemu-riscv@nongnu.org, Rob Herring , Conor Dooley Subject: Re: [PATCH v4 3/4] dt-bindings: riscv: add new riscv,isa strings for emulators Date: Wed, 24 Aug 2022 19:41:46 +0200 Message-ID: <2846981.bB369e8A3T@diego> In-Reply-To: <20220823183319.3314940-4-mail@conchuod.ie> References: <20220823183319.3314940-1-mail@conchuod.ie> <20220823183319.3314940-4-mail@conchuod.ie> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Am Dienstag, 23. August 2022, 20:33:19 CEST schrieb Conor Dooley: > From: Conor Dooley > > The QEMU virt and spike machines currently export a riscv,isa string of > "rv64imafdcsuh", > > While the RISC-V foundation has been ratifying a bunch of extenstions > etc, the kernel has remained relatively static with what hardware is > supported - but the same is not true of QEMU. Using the virt machine > and running dt-validate on the dumped dtb fails, partly due to the > unexpected isa string. > > Rather than enumerate the many many possbilities, change the pattern > to a regex, with the following assumptions: > - ima are required > - the single letter order is fixed & we don't care about things that > can't even do "ima" > - the standard multi letter extensions are all in a "_z" format > where the first letter of is a valid single letter extension > - _s & _h are used for supervisor and hyper visor extensions > - convention says that after the first two chars, a standard multi > letter extension name could be an english word (ifencei anyone?) so > it's not worth restricting the charset > - as the above is just convention, don't apply any charset restrictions > to reduce future churn > - vendor ISA extensions begind with _x and have no charset restrictions > - we don't care about an e extension from an OS pov > - that attempting to validate the contents of the multiletter extensions > with dt-validate beyond the formatting is a futile, massively verbose > or unwieldy exercise at best > > The following limitations also apply: > - multi letter extension ordering is not enforced. dt-schema does not > appear to allow for named match groups, so the resulting regex would > be even more of a headache > - ditto for the numbered extensions That description sounds about right, though me and regexes never became friends, so the following will have to do: Acked-by: Heiko Stuebner > Finally, add me as a maintainer of the binding so that when it breaks > in the future, I can be held responsible! > > Reported-by: Rob Herring > Link: https://lore.kernel.org/linux-riscv/20220803170552.GA2250266-robh@kernel.org/ > Reviewed-by: Andrew Jones > Acked-by: Guo Ren > Signed-off-by: Conor Dooley > --- > Palmer, feel free to drop the maintainer addition. I just mostly want > to clean up my own mess on this when they decide to ratify more > extensions & this comes back up again. > --- > Documentation/devicetree/bindings/riscv/cpus.yaml | 5 ++--- > 1 file changed, 2 insertions(+), 3 deletions(-) > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml > index 873dd12f6e89..90a7cabf58fe 100644 > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > @@ -9,6 +9,7 @@ title: RISC-V bindings for 'cpus' DT nodes > maintainers: > - Paul Walmsley > - Palmer Dabbelt > + - Conor Dooley > > description: | > This document uses some terminology common to the RISC-V community > @@ -79,9 +80,7 @@ properties: > insensitive, letters in the riscv,isa string must be all > lowercase to simplify parsing. > $ref: "/schemas/types.yaml#/definitions/string" > - enum: > - - rv64imac > - - rv64imafdc > + pattern: ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:_[hsxz](?:[a-z])+)*$ > > # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here > timebase-frequency: false >