[PATCH v2 0/6] Correct the number of GPIOs in gpio-ranges for QCS615 and QCS8300

[PATCH v2 0/6] Correct the number of GPIOs in gpio-ranges for QCS615 and QCS8300

[Lijuan Gao]

The UFS_RESET pin on Qualcomm SoCs are controlled by TLMM and exposed
through the GPIO framework. It is expected to be wired to the reset pin
of the primary UFS memory so that the UFS driver can toggle it.

The UFS_RESET pin is exported as GPIOs in addtion to the real GPIOs. The
QCS615 TLMM pin controller has GPIOs 0-122, so correct the gpio-rangs to
124. The QCS8300 TLMM pin controller has GPIOs 0-132, so correct the
gpio-rangs to 134.

Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
---
Changes in v2:
- Update the introductory information in the cover letter
- Update the commit message
- Update the title of the TLMM driver patch
- Link to v1: https://lore.kernel.org/r/20241212-correct_gpio_ranges-v1-0-c5f20d61882f@quicinc.com

---
Lijuan Gao (6):
      dt-bindings: pinctrl: qcom: correct gpio-ranges in examples for qcs615
      dt-bindings: pinctrl: qcom: correct gpio-ranges in examples for qcs8300
      pinctrl: qcom: correct the ngpios entry for QCS615
      pinctrl: qcom: correct the ngpios entry for QCS8300
      arm64: dts: qcom: correct gpio-ranges for QCS615
      arm64: dts: qcom: correct gpio-ranges for QCS8300

 Documentation/devicetree/bindings/pinctrl/qcom,qcs615-tlmm.yaml  | 2 +-
 Documentation/devicetree/bindings/pinctrl/qcom,qcs8300-tlmm.yaml | 2 +-
 arch/arm64/boot/dts/qcom/qcs615.dtsi                             | 2 +-
 arch/arm64/boot/dts/qcom/qcs8300.dtsi                            | 2 +-
 drivers/pinctrl/qcom/pinctrl-qcs615.c                            | 2 +-
 drivers/pinctrl/qcom/pinctrl-qcs8300.c                           | 2 +-
 6 files changed, 6 insertions(+), 6 deletions(-)
---
base-commit: 91e71d606356e50f238d7a87aacdee4abc427f07
change-id: 20241211-correct_gpio_ranges-ed8a25ad22e7

Best regards,
-- 
Lijuan Gao <quic_lijuang@quicinc.com>

[PATCH v2 1/6] dt-bindings: pinctrl: qcom: correct gpio-ranges in examples for qcs615

[Lijuan Gao]

Correct the gpio-ranges in the QCS615 TLMM pin controller example to
include the UFS_RESET pin, which is expected to be wired to the reset
pin of the primary UFS memory. This allows the UFS driver to toggle it.

Fixes: 55c487ea6084 ("dt-bindings: pinctrl: document the QCS615 Top Level Mode Multiplexer")
Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
---
 Documentation/devicetree/bindings/pinctrl/qcom,qcs615-tlmm.yaml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,qcs615-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,qcs615-tlmm.yaml
index 1ce4b5df584a..2791e578c1de 100644
--- a/Documentation/devicetree/bindings/pinctrl/qcom,qcs615-tlmm.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,qcs615-tlmm.yaml
@@ -110,7 +110,7 @@ examples:
               <0x03c00000 0x300000>;
         reg-names = "east", "west", "south";
         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
-        gpio-ranges = <&tlmm 0 0 123>;
+        gpio-ranges = <&tlmm 0 0 124>;
         gpio-controller;
         #gpio-cells = <2>;
         interrupt-controller;

-- 
2.46.0

[PATCH v2 2/6] dt-bindings: pinctrl: qcom: correct gpio-ranges in examples for qcs8300

[Lijuan Gao]

Correct the gpio-ranges in the QCS8300 TLMM pin controller example to
include the UFS_RESET pin, which is expected to be wired to the reset
pin of the primary UFS memory. This allows the UFS driver to toggle it.

Fixes: 5778535972e2 ("dt-bindings: pinctrl: describe qcs8300-tlmm")
Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
---
 Documentation/devicetree/bindings/pinctrl/qcom,qcs8300-tlmm.yaml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,qcs8300-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,qcs8300-tlmm.yaml
index bb0d7132886a..489b41dcc179 100644
--- a/Documentation/devicetree/bindings/pinctrl/qcom,qcs8300-tlmm.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,qcs8300-tlmm.yaml
@@ -106,7 +106,7 @@ examples:
         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
         gpio-controller;
         #gpio-cells = <2>;
-        gpio-ranges = <&tlmm 0 0 133>;
+        gpio-ranges = <&tlmm 0 0 134>;
         interrupt-controller;
         #interrupt-cells = <2>;
 

-- 
2.46.0

[PATCH v2 3/6] pinctrl: qcom: correct the ngpios entry for QCS615

[Lijuan Gao]

Correct the ngpios entry to account for the UFS_RESET pin being exported
as a GPIO in addition to the real GPIOs, allowing the UFS driver to toggle
it.

Fixes: b698f36a9d40 ("pinctrl: qcom: add the tlmm driver for QCS615 platform")
Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
---
 drivers/pinctrl/qcom/pinctrl-qcs615.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pinctrl/qcom/pinctrl-qcs615.c b/drivers/pinctrl/qcom/pinctrl-qcs615.c
index 23015b055f6a..17ca743c2210 100644
--- a/drivers/pinctrl/qcom/pinctrl-qcs615.c
+++ b/drivers/pinctrl/qcom/pinctrl-qcs615.c
@@ -1062,7 +1062,7 @@ static const struct msm_pinctrl_soc_data qcs615_tlmm = {
 	.nfunctions = ARRAY_SIZE(qcs615_functions),
 	.groups = qcs615_groups,
 	.ngroups = ARRAY_SIZE(qcs615_groups),
-	.ngpios = 123,
+	.ngpios = 124,
 	.tiles = qcs615_tiles,
 	.ntiles = ARRAY_SIZE(qcs615_tiles),
 	.wakeirq_map = qcs615_pdc_map,

-- 
2.46.0

[PATCH v2 4/6] pinctrl: qcom: correct the ngpios entry for QCS8300

[Lijuan Gao]

Correct the ngpios entry to account for the UFS_RESET pin, which is
expected to be wired to the reset pin of the primary UFS memory and is
exported as GPIOs in addition to the real GPIOs, allowing the UFS driver
to toggle it.

Fixes: 0c4cd2cc87c8 ("pinctrl: qcom: add the tlmm driver for QCS8300 platforms")
Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
---
 drivers/pinctrl/qcom/pinctrl-qcs8300.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pinctrl/qcom/pinctrl-qcs8300.c b/drivers/pinctrl/qcom/pinctrl-qcs8300.c
index ba6de944a859..5f5f7c4ac644 100644
--- a/drivers/pinctrl/qcom/pinctrl-qcs8300.c
+++ b/drivers/pinctrl/qcom/pinctrl-qcs8300.c
@@ -1204,7 +1204,7 @@ static const struct msm_pinctrl_soc_data qcs8300_pinctrl = {
 	.nfunctions = ARRAY_SIZE(qcs8300_functions),
 	.groups = qcs8300_groups,
 	.ngroups = ARRAY_SIZE(qcs8300_groups),
-	.ngpios = 133,
+	.ngpios = 134,
 	.wakeirq_map = qcs8300_pdc_map,
 	.nwakeirq_map = ARRAY_SIZE(qcs8300_pdc_map),
 	.egpio_func = 11,

-- 
2.46.0

[PATCH v2 5/6] arm64: dts: qcom: correct gpio-ranges for QCS615

[Lijuan Gao]

Correct the gpio-ranges for the QCS615 TLMM pin controller to include
GPIOs 0-122 and the UFS_RESET pin for primary UFS memory reset.

Fixes: 8e266654a2fe ("arm64: dts: qcom: add QCS615 platform")
Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
---
 arch/arm64/boot/dts/qcom/qcs615.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
index c0e4b376a1c6..4c3d8e39ce0b 100644
--- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
@@ -938,7 +938,7 @@ tlmm: pinctrl@3100000 {
 				    "west",
 				    "south";
 			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
-			gpio-ranges = <&tlmm 0 0 123>;
+			gpio-ranges = <&tlmm 0 0 124>;
 			gpio-controller;
 			#gpio-cells = <2>;
 			interrupt-controller;

-- 
2.46.0

[PATCH v2 6/6] arm64: dts: qcom: correct gpio-ranges for QCS8300

[Lijuan Gao]

Correct the gpio-ranges for the QCS8300 TLMM pin controller to include
GPIOs 0-132 and the UFS_RESET pin for primary UFS memory reset.

Fixes: 7be190e4bdd2 ("arm64: dts: qcom: add QCS8300 platform")
Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
---
 arch/arm64/boot/dts/qcom/qcs8300.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
index 73abf2ef9c9f..07d6d3ff4365 100644
--- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
@@ -971,7 +971,7 @@ tlmm: pinctrl@f100000 {
 			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 			gpio-controller;
 			#gpio-cells = <2>;
-			gpio-ranges = <&tlmm 0 0 133>;
+			gpio-ranges = <&tlmm 0 0 134>;
 			interrupt-controller;
 			#interrupt-cells = <2>;
 			wakeup-parent = <&pdc>;

-- 
2.46.0

Re: [PATCH v2 1/6] dt-bindings: pinctrl: qcom: correct gpio-ranges in examples for qcs615

[Krzysztof Kozlowski]

On 19/12/2024 08:59, Lijuan Gao wrote:
> Correct the gpio-ranges in the QCS615 TLMM pin controller example to
> include the UFS_RESET pin, which is expected to be wired to the reset
> pin of the primary UFS memory. This allows the UFS driver to toggle it.
> 
> Fixes: 55c487ea6084 ("dt-bindings: pinctrl: document the QCS615 Top Level Mode Multiplexer")
> Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
> ---

<form letter>
This is a friendly reminder during the review process.

It looks like you received a tag and forgot to add it.

If you do not know the process, here is a short explanation:
Please add Acked-by/Reviewed-by/Tested-by tags when posting new
versions, under or above your Signed-off-by tag. Tag is "received", when
provided in a message replied to you on the mailing list. Tools like b4
can help here. However, there's no need to repost patches *only* to add
the tags. The upstream maintainer will do that for tags received on the
version they apply.

https://elixir.bootlin.com/linux/v6.5-rc3/source/Documentation/process/submitting-patches.rst#L577

If a tag was not added on purpose, please state why and what changed.
</form letter>

Best regards,
Krzysztof

Re: [PATCH v2 1/6] dt-bindings: pinctrl: qcom: correct gpio-ranges in examples for qcs615

[Lijuan Gao]

在 12/19/2024 4:15 PM, Krzysztof Kozlowski 写道:
> On 19/12/2024 08:59, Lijuan Gao wrote:
>> Correct the gpio-ranges in the QCS615 TLMM pin controller example to
>> include the UFS_RESET pin, which is expected to be wired to the reset
>> pin of the primary UFS memory. This allows the UFS driver to toggle it.
>>
>> Fixes: 55c487ea6084 ("dt-bindings: pinctrl: document the QCS615 Top Level Mode Multiplexer")
>> Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
>> ---
> 
> <form letter>
> This is a friendly reminder during the review process.
> 
> It looks like you received a tag and forgot to add it.
> 
> If you do not know the process, here is a short explanation:
> Please add Acked-by/Reviewed-by/Tested-by tags when posting new
> versions, under or above your Signed-off-by tag. Tag is "received", when
> provided in a message replied to you on the mailing list. Tools like b4
> can help here. However, there's no need to repost patches *only* to add
> the tags. The upstream maintainer will do that for tags received on the
> version they apply.
> 
> https://elixir.bootlin.com/linux/v6.5-rc3/source/Documentation/process/submitting-patches.rst#L577
> 
> If a tag was not added on purpose, please state why and what changed.
> </form letter>
Sorry, my mistake. I didn't realize that Rob Herring had already given 
me an "Acked-by." I updated the commit message in this patch.
> 
> Best regards,
> Krzysztof

-- 
Thx and BRs
Lijuan Gao

Re: [PATCH v2 3/6] pinctrl: qcom: correct the ngpios entry for QCS615

[Konrad Dybcio]

On 19.12.2024 8:59 AM, Lijuan Gao wrote:
> Correct the ngpios entry to account for the UFS_RESET pin being exported
> as a GPIO in addition to the real GPIOs, allowing the UFS driver to toggle
> it.
> 
> Fixes: b698f36a9d40 ("pinctrl: qcom: add the tlmm driver for QCS615 platform")
> Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

Re: [PATCH v2 4/6] pinctrl: qcom: correct the ngpios entry for QCS8300

[Konrad Dybcio]

On 19.12.2024 8:59 AM, Lijuan Gao wrote:
> Correct the ngpios entry to account for the UFS_RESET pin, which is
> expected to be wired to the reset pin of the primary UFS memory and is
> exported as GPIOs in addition to the real GPIOs, allowing the UFS driver
> to toggle it.
> 
> Fixes: 0c4cd2cc87c8 ("pinctrl: qcom: add the tlmm driver for QCS8300 platforms")
> Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

Re: [PATCH v2 5/6] arm64: dts: qcom: correct gpio-ranges for QCS615

[Konrad Dybcio]

On 19.12.2024 8:59 AM, Lijuan Gao wrote:
> Correct the gpio-ranges for the QCS615 TLMM pin controller to include
> GPIOs 0-122 and the UFS_RESET pin for primary UFS memory reset.
> 
> Fixes: 8e266654a2fe ("arm64: dts: qcom: add QCS615 platform")
> Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

Re: [PATCH v2 6/6] arm64: dts: qcom: correct gpio-ranges for QCS8300

[Konrad Dybcio]

On 19.12.2024 8:59 AM, Lijuan Gao wrote:
> Correct the gpio-ranges for the QCS8300 TLMM pin controller to include
> GPIOs 0-132 and the UFS_RESET pin for primary UFS memory reset.
> 
> Fixes: 7be190e4bdd2 ("arm64: dts: qcom: add QCS8300 platform")
> Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

Re: [PATCH v2 0/6] Correct the number of GPIOs in gpio-ranges for QCS615 and QCS8300

[Linus Walleij]

Hi Lijuan,

thanks for your patches!

On Thu, Dec 19, 2024 at 9:00 AM Lijuan Gao <quic_lijuang@quicinc.com> wrote:

> The UFS_RESET pin on Qualcomm SoCs are controlled by TLMM and exposed
> through the GPIO framework. It is expected to be wired to the reset pin
> of the primary UFS memory so that the UFS driver can toggle it.
>
> The UFS_RESET pin is exported as GPIOs in addtion to the real GPIOs. The
> QCS615 TLMM pin controller has GPIOs 0-122, so correct the gpio-rangs to
> 124. The QCS8300 TLMM pin controller has GPIOs 0-132, so correct the
> gpio-rangs to 134.
(...)
> Lijuan Gao (6):
>       dt-bindings: pinctrl: qcom: correct gpio-ranges in examples for qcs615
>       dt-bindings: pinctrl: qcom: correct gpio-ranges in examples for qcs8300
>       pinctrl: qcom: correct the ngpios entry for QCS615
>       pinctrl: qcom: correct the ngpios entry for QCS8300

I'm planning to apply these 4 after v3 arrives with the collected ACKs etc.

Yours,
Linus Walleij

Re: (subset) [PATCH v2 0/6] Correct the number of GPIOs in gpio-ranges for QCS615 and QCS8300

[Bjorn Andersson]

On Thu, 19 Dec 2024 15:59:42 +0800, Lijuan Gao wrote:
> The UFS_RESET pin on Qualcomm SoCs are controlled by TLMM and exposed
> through the GPIO framework. It is expected to be wired to the reset pin
> of the primary UFS memory so that the UFS driver can toggle it.
> 
> The UFS_RESET pin is exported as GPIOs in addtion to the real GPIOs. The
> QCS615 TLMM pin controller has GPIOs 0-122, so correct the gpio-rangs to
> 124. The QCS8300 TLMM pin controller has GPIOs 0-132, so correct the
> gpio-rangs to 134.
> 
> [...]

Applied, thanks!

[5/6] arm64: dts: qcom: correct gpio-ranges for QCS615
      commit: 80c82827327d80bde8fc96ebd4e637d0454062db
[6/6] arm64: dts: qcom: correct gpio-ranges for QCS8300
      commit: c57c39ee522d873db2cb23486581a8269c389cfe

Best regards,
-- 
Bjorn Andersson <andersson@kernel.org>