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charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzIyMDE4NCBTYWx0ZWRfX1fqheyjcn2hi nKzrWBz/79ZHz+xWfIhVodlaNTjHu5Rb0UFRJF1hVWcsCMd+VPhBfkJdUwSLudj5S+afcKv8ktG mZP/zecyHXgOkuLGRxwjzHZFv90RLXzYs/RuqOyI99MWw/b39HMcGXQotncXLNVcrTVBiACPf8Y X7j7EmE0HDs6kfSiGdG0ZzJ02iL6KOQ0IM7goewpR348dbmhM8EPcnm8EyAMMHHLIJ5XHkPWm+a np+GuRrjXtjMLLtuzgWW1DQi6AJWsyRB20JbCQW1Ryl1NYMFPie828SHAnav5WeNNFVZ5GTxQuj rHPKRdWSjCt5vb2V9hMJjxSzSfkuRATABUlG+roO4Q/wwWYhRVfUXeyTSUIsSICdRnyNV7a27rq uXj+rZ43uWfZOQYBCiNs+z6GMv0jbM81Ry1uIII+xCiPHrmpPnKU/4xmCKo7APpXWw43Ou8B X-Proofpoint-ORIG-GUID: 1tjuW8uWVc77HuOmZ0Ozslpz_ggkxfc5 X-Proofpoint-GUID: 1tjuW8uWVc77HuOmZ0Ozslpz_ggkxfc5 X-Authority-Analysis: v=2.4 cv=OPUn3TaB c=1 sm=1 tr=0 ts=688003b1 cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=4dphQItTPUswyQvINXrzgA==:17 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=EUspDBNiAAAA:8 a=e3cV7b4uTqknVPGEt5AA:9 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-22_03,2025-07-22_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 clxscore=1015 mlxlogscore=924 lowpriorityscore=0 suspectscore=0 spamscore=0 mlxscore=0 bulkscore=0 priorityscore=1501 phishscore=0 malwarescore=0 impostorscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507220184 On 7/22/2025 7:22 PM, Dmitry Baryshkov wrote: > On Sun, Jul 20, 2025 at 05:46:14PM +0530, Akhil P Oommen wrote: >> From the hangcheck handler, KMD checks a few registers in GX >> domain to see if the GPU made any progress. But it cannot access >> those registers when IFPC is enabled. Since HW based hang detection >> is pretty decent, lets rely on it instead of these registers when >> IFPC is enabled. >> >> Signed-off-by: Akhil P Oommen >> --- >> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 14 ++++++++++++-- >> 1 file changed, 12 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >> index e331cbdb117df6cfa8ae0e4c44a5aa91ba93f8eb..b3becb230a94163cccff4eaffb8eed44f1c29ad0 100644 >> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >> @@ -2399,13 +2399,23 @@ static uint32_t a6xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) >> >> static bool a6xx_progress(struct msm_gpu *gpu, struct msm_ringbuffer *ring) >> { >> - struct msm_cp_state cp_state = { >> + struct msm_cp_state cp_state; >> + bool progress; >> + >> + /* >> + * With IFPC, KMD doesn't know whether GX power domain is collapsed or not. So, we can't >> + * blindly read the below registers in GX domain. Lets trust the hang detection in HW and >> + * lie to the caller that there was progress. > > I know that we've relaxed code line width to 100 chars. Would it be > possible to reformat the comment to 72-75 chars? Yeah, makes sense for multi-line comments. Shouldn't the limit be 80? -Akhil > >> + */ >> + if (to_adreno_gpu(gpu)->info->quirks & ADRENO_QUIRK_IFPC) >> + return true; >> + >> + cp_state = (struct msm_cp_state) { >> .ib1_base = gpu_read64(gpu, REG_A6XX_CP_IB1_BASE), >> .ib2_base = gpu_read64(gpu, REG_A6XX_CP_IB2_BASE), >> .ib1_rem = gpu_read(gpu, REG_A6XX_CP_IB1_REM_SIZE), >> .ib2_rem = gpu_read(gpu, REG_A6XX_CP_IB2_REM_SIZE), >> }; >> - bool progress; >> >> /* >> * Adjust the remaining data to account for what has already been >> >> -- >> 2.50.1 >> >