[RFC PATCH v2 34/34] x86/msr: Convert native_rdmsr_no_trace() uses to native_rdmsrq_no_trace() uses

Xin Li (Intel)
2025-04-22T08:23:58Z

Convert native_rdmsr_no_trace() uses to native_rdmsrq_no_trace() uses
cleanly with the use of struct msr, and remove native_rdmsr_no_trace().

Signed-off-by: Xin Li (Intel) <xin@zytor.com>
---
arch/x86/include/asm/microcode.h | 6 +++---
arch/x86/include/asm/msr.h | 13 +++----------
arch/x86/kernel/cpu/microcode/amd.c | 8 ++------
arch/x86/kernel/cpu/microcode/core.c | 4 ++--
arch/x86/kernel/cpu/microcode/intel.c | 6 +++---
5 files changed, 13 insertions(+), 24 deletions(-)

diff --git a/arch/x86/include/asm/microcode.h b/arch/x86/include/asm/microcode.h
index d581fdaf1f36..1d9641349744 100644
--- a/arch/x86/include/asm/microcode.h
+++ b/arch/x86/include/asm/microcode.h
@@ -61,7 +61,7 @@ static inline int intel_microcode_get_datasize(struct microcode_header_intel *hd

static inline u32 intel_get_microcode_revision(void)
{
- u32 rev, dummy;
+ struct msr val;

native_wrmsrq_no_trace(MSR_IA32_UCODE_REV, 0);

@@ -69,9 +69,9 @@ static inline u32 intel_get_microcode_revision(void)
native_cpuid_eax(1);

/* get the current revision from MSR 0x8B */
- native_rdmsr_no_trace(MSR_IA32_UCODE_REV, dummy, rev);
+ val.q = native_rdmsrq_no_trace(MSR_IA32_UCODE_REV);

- return rev;
+ return val.h;
}
#endif /* !CONFIG_CPU_SUP_INTEL */

diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h
index be593a15a838..aebcd846af3e 100644
--- a/arch/x86/include/asm/msr.h
+++ b/arch/x86/include/asm/msr.h
@@ -141,9 +141,9 @@ static __always_inline bool is_msr_imm_insn(void *ip)
* / \ |
* / \ |
* native_rdmsrq_no_trace() native_rdmsrq_safe() |
- * / \ |
- * / \ |
- * native_rdmsr_no_trace() native_rdmsrq() |
+ * / |
+ * / |
+ * native_rdmsrq() |
* |
* |
* |
@@ -239,13 +239,6 @@ static __always_inline u64 native_rdmsrq_no_trace(u32 msr)
return val;
}

-#define native_rdmsr_no_trace(msr, low, high) \
-do { \
- u64 __val = native_rdmsrq_no_trace(msr); \
- (void)((low) = (u32)__val); \
- (void)((high) = (u32)(__val >> 32)); \
-} while (0)
-
static inline u64 native_rdmsrq(u32 msr)
{
u64 val = native_rdmsrq_no_trace(msr);
diff --git a/arch/x86/kernel/cpu/microcode/amd.c b/arch/x86/kernel/cpu/microcode/amd.c
index f1f275ddab57..b4d66e79089c 100644
--- a/arch/x86/kernel/cpu/microcode/amd.c
+++ b/arch/x86/kernel/cpu/microcode/amd.c
@@ -254,11 +254,7 @@ static bool verify_sha256_digest(u32 patch_id, u32 cur_rev, const u8 *data, unsi

static u32 get_patch_level(void)
{
- u32 rev, dummy __always_unused;
-
- native_rdmsr_no_trace(MSR_AMD64_PATCH_LEVEL, rev, dummy);
-
- return rev;
+ return native_rdmsrq_no_trace(MSR_AMD64_PATCH_LEVEL);
}

static union cpuid_1_eax ucode_rev_to_cpuid(unsigned int val)
@@ -835,7 +831,7 @@ static struct ucode_patch *find_patch(unsigned int cpu)

void reload_ucode_amd(unsigned int cpu)
{
- u32 rev, dummy __always_unused;
+ u32 rev;
struct microcode_amd *mc;
struct ucode_patch *p;

diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/microcode/core.c
index 9bda8fd987ab..81b264373d3e 100644
--- a/arch/x86/kernel/cpu/microcode/core.c
+++ b/arch/x86/kernel/cpu/microcode/core.c
@@ -81,10 +81,10 @@ struct early_load_data early_data;
*/
static bool amd_check_current_patch_level(void)
{
- u32 lvl, dummy, i;
+ u32 lvl, i;
u32 *levels;

- native_rdmsr_no_trace(MSR_AMD64_PATCH_LEVEL, lvl, dummy);
+ lvl = native_rdmsrq_no_trace(MSR_AMD64_PATCH_LEVEL);

levels = final_levels;

diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c
index c0307b1ad63d..1b484214f3ee 100644
--- a/arch/x86/kernel/cpu/microcode/intel.c
+++ b/arch/x86/kernel/cpu/microcode/intel.c
@@ -75,11 +75,11 @@ void intel_collect_cpu_info(struct cpu_signature *sig)
sig->rev = intel_get_microcode_revision();

if (IFM(x86_family(sig->sig), x86_model(sig->sig)) >= INTEL_PENTIUM_III_DESCHUTES) {
- unsigned int val[2];
+ struct msr val;

/* get processor flags from MSR 0x17 */
- native_rdmsr_no_trace(MSR_IA32_PLATFORM_ID, val[0], val[1]);
- sig->pf = 1 << ((val[1] >> 18) & 7);
+ val.q = native_rdmsrq_no_trace(MSR_IA32_PLATFORM_ID);
+ sig->pf = 1 << ((val.h >> 18) & 7);
}
}
EXPORT_SYMBOL_GPL(intel_collect_cpu_info);
--
2.49.0