Re: [RFC PATCH v2 14/34] x86/msr: refactor pv_cpu_ops.write_msr{_safe}()

Jürgen Groß
2025-04-24T10:16:25Z

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On 22.04.25 10:21, Xin Li (Intel) wrote:
> An MSR value is represented as a 64-bit unsigned integer, with existing
> MSR instructions storing it in EDX:EAX as two 32-bit segments.
>
> The new immediate form MSR instructions, however, utilize a 64-bit
> general-purpose register to store the MSR value. To unify the usage of
> all MSR instructions, let the default MSR access APIs accept an MSR
> value as a single 64-bit argument instead of two 32-bit segments.
>
> The dual 32-bit APIs are still available as convenient wrappers over the
> APIs that handle an MSR value as a single 64-bit argument.
>
> The following illustrates the updated derivation of the MSR write APIs:
>
> __wrmsrq(u32 msr, u64 val)
> / \
> / \
> native_wrmsrq(msr, val) native_wrmsr(msr, low, high)
> |
> |
> native_write_msr(msr, val)
> / \
> / \
> wrmsrq(msr, val) wrmsr(msr, low, high)
>
> When CONFIG_PARAVIRT is enabled, wrmsrq() and wrmsr() are defined on top
> of paravirt_write_msr():
>
> paravirt_write_msr(u32 msr, u64 val)
> / \
> / \
> wrmsrq(msr, val) wrmsr(msr, low, high)
>
> paravirt_write_msr() invokes cpu.write_msr(msr, val), an indirect layer
> of pv_ops MSR write call:
>
> If on native:
>
> cpu.write_msr = native_write_msr
>
> If on Xen:
>
> cpu.write_msr = xen_write_msr
>
> Therefore, refactor pv_cpu_ops.write_msr{_safe}() to accept an MSR value
> in a single u64 argument, replacing the current dual u32 arguments.
>
> No functional change intended.
>
> Signed-off-by: Xin Li (Intel) <xin@zytor.com>

Reviewed-by: Juergen Gross <jgross@suse.com>

Juergen

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