[RFC PATCH v2 30/34] x86/msr: Rename native_rdmsr() to native_rdmsr_no_trace()

Xin Li (Intel)
2025-04-22T08:23:49Z

native_rdmsr() doesn't do trace thus can be used in noinstr context,
rename it to native_rdmsr_no_trace() to make it explicit.

Signed-off-by: Xin Li (Intel) <xin@zytor.com>
---
arch/x86/include/asm/microcode.h | 2 +-
arch/x86/include/asm/msr.h | 8 ++++----
arch/x86/kernel/cpu/microcode/amd.c | 2 +-
arch/x86/kernel/cpu/microcode/core.c | 2 +-
arch/x86/kernel/cpu/microcode/intel.c | 2 +-
5 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/arch/x86/include/asm/microcode.h b/arch/x86/include/asm/microcode.h
index da482f430d80..d581fdaf1f36 100644
--- a/arch/x86/include/asm/microcode.h
+++ b/arch/x86/include/asm/microcode.h
@@ -69,7 +69,7 @@ static inline u32 intel_get_microcode_revision(void)
native_cpuid_eax(1);

/* get the current revision from MSR 0x8B */
- native_rdmsr(MSR_IA32_UCODE_REV, dummy, rev);
+ native_rdmsr_no_trace(MSR_IA32_UCODE_REV, dummy, rev);

return rev;
}
diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h
index 050d750a5ab7..dfaac42b6258 100644
--- a/arch/x86/include/asm/msr.h
+++ b/arch/x86/include/asm/msr.h
@@ -158,9 +158,9 @@ static __always_inline bool is_msr_imm_insn(void *ip)
* / \ |
* / \ |
* native_rdmsrq_no_trace() native_read_msr_safe() |
- * / \ |
- * / \ |
- * native_rdmsr() native_read_msr() |
+ * / \ |
+ * / \ |
+ * native_rdmsr_no_trace() native_read_msr() |
* |
* |
* |
@@ -256,7 +256,7 @@ static __always_inline u64 native_rdmsrq_no_trace(u32 msr)
return val;
}

-#define native_rdmsr(msr, low, high) \
+#define native_rdmsr_no_trace(msr, low, high) \
do { \
u64 __val = native_rdmsrq_no_trace(msr); \
(void)((low) = (u32)__val); \
diff --git a/arch/x86/kernel/cpu/microcode/amd.c b/arch/x86/kernel/cpu/microcode/amd.c
index 41c553396500..f1f275ddab57 100644
--- a/arch/x86/kernel/cpu/microcode/amd.c
+++ b/arch/x86/kernel/cpu/microcode/amd.c
@@ -256,7 +256,7 @@ static u32 get_patch_level(void)
{
u32 rev, dummy __always_unused;

- native_rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);
+ native_rdmsr_no_trace(MSR_AMD64_PATCH_LEVEL, rev, dummy);

return rev;
}
diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/microcode/core.c
index b3658d11e7b6..9bda8fd987ab 100644
--- a/arch/x86/kernel/cpu/microcode/core.c
+++ b/arch/x86/kernel/cpu/microcode/core.c
@@ -84,7 +84,7 @@ static bool amd_check_current_patch_level(void)
u32 lvl, dummy, i;
u32 *levels;

- native_rdmsr(MSR_AMD64_PATCH_LEVEL, lvl, dummy);
+ native_rdmsr_no_trace(MSR_AMD64_PATCH_LEVEL, lvl, dummy);

levels = final_levels;

diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c
index 26e13dc4cedd..c0307b1ad63d 100644
--- a/arch/x86/kernel/cpu/microcode/intel.c
+++ b/arch/x86/kernel/cpu/microcode/intel.c
@@ -78,7 +78,7 @@ void intel_collect_cpu_info(struct cpu_signature *sig)
unsigned int val[2];

/* get processor flags from MSR 0x17 */
- native_rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]);
+ native_rdmsr_no_trace(MSR_IA32_PLATFORM_ID, val[0], val[1]);
sig->pf = 1 << ((val[1] >> 18) & 7);
}
}
--
2.49.0