Re: [PATCH v6 6/6] cxl/pci: Add trace logging for CXL PCIe Port RAS errors

Dan Williams
2025-02-05T23:06:51Z

Smita Koralahalli wrote:
> The CXL drivers use kernel trace functions for logging endpoint and
> Restricted CXL host (RCH) Downstream Port RAS errors. Similar functionality
> is required for CXL Root Ports, CXL Downstream Switch Ports, and CXL
> Upstream Switch Ports.
>
> Introduce trace logging functions for both RAS correctable and
> uncorrectable errors specific to CXL PCIe Ports. Use them to trace
> FW-First Protocol errors.
>
> Co-developed-by: Terry Bowman <terry.bowman@amd.com>
> Signed-off-by: Terry Bowman <terry.bowman@amd.com>
> Signed-off-by: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com>

I think this functionality moves to a central / non-cxl_pci location
once we have a formal CXL AER path established.

So, for this series you can add my Reviewed-by: to patches 1-4, but I am
not yet convinced cxl_pci should play a role in emitting protocol errors
compared to a centralized place in the core.