From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751408AbcFNPUj (ORCPT ); Tue, 14 Jun 2016 11:20:39 -0400 Received: from gloria.sntech.de ([95.129.55.99]:36239 "EHLO gloria.sntech.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751190AbcFNPUi (ORCPT ); Tue, 14 Jun 2016 11:20:38 -0400 From: Heiko =?ISO-8859-1?Q?St=FCbner?= To: Guenter Roeck Cc: Frank Wang , dianders@chromium.org, groeck@chromium.org, jwerner@chromium.org, kishon@ti.com, robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-usb@vger.kernel.org, linux-rockchip@lists.infradead.org, xzy.xu@rock-chips.com, kever.yang@rock-chips.com, huangtao@rock-chips.com, william.wu@rock-chips.com Subject: Re: [PATCH v5 2/2] phy: rockchip-inno-usb2: add a new driver for Rockchip usb2phy Date: Tue, 14 Jun 2016 17:20:14 +0200 Message-ID: <2983992.DFFWV4P4jo@diego> User-Agent: KMail/4.14.10 (Linux/4.5.0-2-amd64; KDE/4.14.14; x86_64; ; ) In-Reply-To: <57601A1D.9020803@roeck-us.net> References: <1465783810-18756-1-git-send-email-frank.wang@rock-chips.com> <1465783810-18756-3-git-send-email-frank.wang@rock-chips.com> <57601A1D.9020803@roeck-us.net> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Am Dienstag, 14. Juni 2016, 07:52:13 schrieb Guenter Roeck: > On 06/12/2016 07:10 PM, Frank Wang wrote: > > The newer SoCs (rk3366, rk3399) take a different usb-phy IP block > > than rk3288 and before, and most of phy-related registers are also > > different from the past, so a new phy driver is required necessarily. > > > > Signed-off-by: Frank Wang > > --- > > [ ... ] > > > + > > +static int rockchip_usb2phy_resume(struct phy *phy) > > +{ > > + struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy); > > + struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent); > > + int ret; > > + > > + dev_dbg(&rport->phy->dev, "port resume\n"); > > + > > + ret = clk_prepare_enable(rphy->clk480m); > > + if (ret) > > + return ret; > > + > > + ret = property_enable(rphy, &rport->port_cfg->phy_sus, false); > > + if (ret) > > + return ret; > > + > > + rport->suspended = false; > > + return 0; > > +} > > + > > +static int rockchip_usb2phy_suspend(struct phy *phy) > > +{ > > + struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy); > > + struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent); > > + int ret; > > + > > + dev_dbg(&rport->phy->dev, "port suspend\n"); > > + > > + ret = property_enable(rphy, &rport->port_cfg->phy_sus, true); > > + if (ret) > > + return ret; > > + > > + rport->suspended = true; > > + clk_disable_unprepare(rphy->clk480m); > > + return 0; > > +} > > + > > I am still quite confused by the clock handling. > > The above will be called for each instantiated phy (user, otg). > Each time, clk_disable_unprepare() will be called. Yet, there > is no matching clk_prepare_enable() call during initialization. > > How does this work ? the created clock gets the supplying clock as parent, see + rphy->clk = of_clk_get_by_name(node, "phyclk"); + if (IS_ERR(rphy->clk)) { + rphy->clk = NULL; + init.parent_names = NULL; + init.num_parents = 0; + } else { + clk_name = __clk_get_name(rphy->clk); + init.parent_names = &clk_name; + init.num_parents = 1; + } that way when you enable the 480m clock from the phy, its parent will automatically get enabled as well. And of course due to refcounting in the clock framework, the 480m clock (and thus also its parent) will only get disabled once both the host and otg port have disabled it.