From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from out-173.mta0.migadu.com (out-173.mta0.migadu.com [91.218.175.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 56DC53233F4 for ; Wed, 6 May 2026 22:43:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.218.175.173 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778107409; cv=none; b=dUOaWwTEkBdWfflVSq4/vusKyHAGJmMrR1/wr4TCu/XaRjzJFyyH8VHwJuV5tThIdh8AYqYxR/rdnouQjwUdLM6UMBn4dEYrt1tlU9YOek5RwzWpi5e+esLaG3QHwCcXiQ9TBQmezdIUfZosGbudGHbm6v7w9dGlHfr4et/Ma3s= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778107409; c=relaxed/simple; bh=tixKAEDJAnYdVt3di29GXUTaszKwxFSltvbjtrfu3uc=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=EZFfIyEhaRvvKzCz3SVccn/N7J+MG0TzQKbzw8dUoC11jWV/dCIBNRyWv0eCdEB4pgLfQhO0rNQ7DIUl12FTmTSBNPeXnKRFTAoxS72B0bDuJ/jyRavqU4JEBuf5pjS6jv2ky78yBbOwmAGDHTKQodms9gRuoomTAfv1+dy92A0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=uWUB+XW7; arc=none smtp.client-ip=91.218.175.173 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="uWUB+XW7" Message-ID: <2a15199c-d48f-4034-a907-6efa883d5d99@linux.dev> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1778107403; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=yURQSTjJQ+qtbFe3jellE7Q5DOMcjnDhP6Zyx8QZf7w=; b=uWUB+XW7QNy+t0c5a8ftjrI2v2EcXg2o0Hla2P7R52SadZ7zoeb5GnylS/VJBDmCL2sDIl t8TZ6ubt3gSz0uiQglvNMC4GORponHP9vhxzZlkdHNOpzMQ2tpmzIZT4DD3a7lpy8dPZh2 SUb6RWrCnG2FpUR/suDy6EcNG7slaVo= Date: Wed, 6 May 2026 23:43:19 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Subject: Re: [PATCH net-next 6/9] net: atlantic: implement AQC113 L2/L3/L4 RX filter management filter management management To: sukhdeeps@marvell.com, netdev@vger.kernel.org Cc: irusskikh@marvell.com, epomozov@marvell.com, richardcochran@gmail.com, andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, linux-kernel@vger.kernel.org References: <20260506135706.2834-1-sukhdeeps@marvell.com> <20260506135706.2834-7-sukhdeeps@marvell.com> Content-Language: en-US X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. From: Vadim Fedorenko In-Reply-To: <20260506135706.2834-7-sukhdeeps@marvell.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Migadu-Flow: FLOW_OUT On 06/05/2026 14:57, sukhdeeps@marvell.com wrote: > From: Sukhdeep Singh > > Implement complete RX filter management for AQC113 hardware: > > - Add tag-based filter policy with reference-counted sharing, allowing > multiple filter rules to share the same L3 or L4 hardware filter > when their match criteria are identical. > - Implement L3 (IPv4/IPv6 source/destination address and protocol) > filter find, get (program HW and increment refcount), and put > (decrement refcount and clear HW when last user releases). > - Implement L4 (TCP/UDP/SCTP source/destination port) filter > management with the same find/get/put pattern. > - Add combined L3L4 filter configuration that translates legacy > aq_rx_filter_l3l4 commands into AQC113 separate L3+L4 filter > programming with Action Resolver Table (ART) entries. > - Add L2 ethertype filter set/clear with tag-based ART integration. > - Add MAC address setup using firmware-provided L2 filter base index. > > Update hardware initialization: > - Use firmware-reported ART section base and count instead of > hardcoded 0xFFFF section enable. > - Enable L3 v6/v4 select mode for simultaneous IPv4/IPv6 filtering. > - Initialize L3L4 filter indices to -1 on reset. > > Wire up hw_filter_l2_set, hw_filter_l2_clear, hw_filter_l3l4_set, > hw_set_mac_address, hw_get_version, and hw_get_regs in hw_atl2_ops. > > Signed-off-by: Sukhdeep Singh > --- > .../net/ethernet/aquantia/atlantic/aq_hw.h | 2 + > .../aquantia/atlantic/hw_atl2/hw_atl2.c | 582 +++++++++++++++++- > 2 files changed, 580 insertions(+), 4 deletions(-) [...] > > @@ -380,6 +422,9 @@ static void hw_atl2_hw_init_new_rx_filters(struct aq_hw_s *self) > { > u8 *prio_tc_map = self->aq_nic_cfg->prio_tc_map; > struct hw_atl2_priv *priv = self->priv; > + u32 art_first_sec, art_last_sec; > + u32 art_sections; > + u32 art_mask = 0; no need to init variable which is overwritten later ... > u16 action; > u8 index; > int i; > @@ -394,9 +439,14 @@ static void hw_atl2_hw_init_new_rx_filters(struct aq_hw_s *self) > * REC entry is used for further processing. If multiple entries match, > * the lowest REC entry, Action field will be selected. > */ > - hw_atl2_rpf_act_rslvr_section_en_set(self, 0xFFFF); > + art_last_sec = priv->art_base_index / 8 + priv->art_count / 8; > + art_first_sec = priv->art_base_index / 8; > + art_mask = (BIT(art_last_sec) - 1) - (BIT(art_first_sec) - 1); ... here > + art_sections = hw_atl2_rpf_act_rslvr_section_en_get(self) | art_mask; > + hw_atl2_rpf_act_rslvr_section_en_set(self, art_sections); > + hw_atl2_rpf_l3_v6_v4_select_set(self, 1); > hw_atl2_rpfl2_uc_flr_tag_set(self, HW_ATL2_RPF_TAG_BASE_UC, > - HW_ATL2_MAC_UC); > + priv->l2_filters_base_index); > hw_atl2_rpfl2_bc_flr_tag_set(self, HW_ATL2_RPF_TAG_BASE_UC); > > /* FW reserves the beginning of ART, thus all driver entries must > @@ -530,6 +580,35 @@ static int hw_atl2_hw_init_rx_path(struct aq_hw_s *self) > return aq_hw_err_from_flags(self); > } > > +static int hw_atl2_hw_mac_addr_set(struct aq_hw_s *self, const u8 *mac_addr) > +{ > + struct hw_atl2_priv *priv = self->priv; > + u32 location = priv->l2_filters_base_index; > + unsigned int h = 0U; > + unsigned int l = 0U; > + int err = 0; here again, h, l and err are not used with init values. > + > + if (!mac_addr) { > + err = -EINVAL; > + goto err_exit; > + } > + h = (mac_addr[0] << 8) | (mac_addr[1]); > + l = (mac_addr[2] << 24) | (mac_addr[3] << 16) | > + (mac_addr[4] << 8) | mac_addr[5]; > + > + hw_atl_rpfl2_uc_flr_en_set(self, 0U, location); > + hw_atl_rpfl2unicast_dest_addresslsw_set(self, l, location); > + hw_atl_rpfl2unicast_dest_addressmsw_set(self, h, location); > + hw_atl_rpfl2unicast_flr_act_set(self, 1U, location); > + hw_atl2_rpfl2_uc_flr_tag_set(self, HW_ATL2_RPF_TAG_BASE_UC, location); > + hw_atl_rpfl2_uc_flr_en_set(self, 1U, location); > + > + err = aq_hw_err_from_flags(self); > + > +err_exit: > + return err; > +} > + > static int hw_atl2_hw_init(struct aq_hw_s *self, const u8 *mac_addr) > { > static u32 aq_hw_atl2_igcr_table_[4][2] = { [...]