Re: [PATCH v5 2/7] scsi: ufs-qcom: Add reset control support for host controller

Vinod Koul
2019-12-18T04:12:07Z

On 18-12-19, 02:44, cang@codeaurora.org wrote:

> Hi Vinod and Jeffrey,
>
> Let me summary here, now the 1000000us timeout works for both 845 and 8998.
> However, 8150 still fails.
>
> > > The bigger question is why is the reset causing the timeout to be
> > > increased for sdm845 and not to work in case of sm8150! (Vinod)
>
> I would not say this patch increases the timeout. With this patch,
> the PCS polling timeout, per my profiling, the PCS ready usually needs
> less than 5000us, which is the actual time needed for PCS bit to be ready.
>
> The reason why 1000us worked for you is because, w/o the patch, UFS PHY
> registers are retained from pre-kernel stage (bootloader i.e.), the PCS
> ready
> bit was set to 1 in pre-kernel stage, so when kernel driver reads it, it
> returns
> 1, not even to be polled at all. It may seem "faster", but not the right
> thing to do, because kernel stage may need different PHY settings than
> pre-kernel stage, keeping the settings configured in pre-kernel stage is not
> always right, so this patch is needed. And increasing 1000us to 1000000us
> is the right thing to do, but not a hack.
>
> As reg for the phy initialization timeout on 8150, I found there is
> something
> wrong with its settings in /drivers/phy/qualcomm/phy-qcom-qmp.c
>
> static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = {
> QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x01),
> QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9),
>
> "QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x01)" should NOT appear in the
> serdes
> table! I haven't check who made this change, but please have a try after
> remove
> this line from sm8150_ufsphy_serdes_tbl.

That is me :) Looks like I made an error while porting from downstream. I
did a quick check to remove this and it doesn't work yet, let me recheck
the settings again ...

Thanks for your help!

--
~Vinod