From: Dave Jiang <dave.jiang@intel.com>
To: Terry Bowman <terry.bowman@amd.com>,
dave@stgolabs.net, jonathan.cameron@huawei.com,
alison.schofield@intel.com, dan.j.williams@intel.com,
bhelgaas@google.com, shiju.jose@huawei.com, ming.li@zohomail.com,
Smita.KoralahalliChannabasappa@amd.com, rrichter@amd.com,
dan.carpenter@linaro.org, PradeepVineshReddy.Kodamati@amd.com,
lukas@wunner.de, Benjamin.Cheatham@amd.com,
sathyanarayanan.kuppuswamy@linux.intel.com,
linux-cxl@vger.kernel.org, vishal.l.verma@intel.com,
alucerop@amd.com, ira.weiny@intel.com
Cc: linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org
Subject: Re: [PATCH v16 02/10] PCI/CXL: Update unregistration for AER-CXL and CPER-CXL kfifos
Date: Mon, 9 Mar 2026 11:30:29 -0700 [thread overview]
Message-ID: <2bb59ea6-9d33-4dfe-91de-644e20da6307@intel.com> (raw)
In-Reply-To: <20260302203648.2886956-3-terry.bowman@amd.com>
On 3/2/26 1:36 PM, Terry Bowman wrote:
> The current AER-CXL kfifo unregistration does not cancel pending work after
> clearing the work function pointer. In addition, cancel_work_sync() is
> called on behalf of the CPER-CXL kfifo in cxl_ras_exit() and should be
> moved into the kfifo deregistration function.
>
> Add logic to cancel the AER-CXL kfifo's pending work in
> cxl_unregister_proto_err_work().
>
> Move the CPER-CXL kfifo cancel call from cxl_ras_exit() to
> cxl_cper_unregister_prot_err_work(). Release the CPER-CXL spinlock
> before calling cancel_work_sync() to avoid deadlock.
>
> In both kfifo unregistration cases, add the necessary synchronization
> to enforce proper lock ordering: protect pointer updates under the
> lock, and clear the work pointer, then cancel any outstanding work
> after the lock is released.
>
> Link: https://lore.kernel.org/linux-cxl/6982ca54e094b_55fa1005@dwillia2-mobl4.notmuch/
> Signed-off-by: Terry Bowman <terry.bowman@amd.com>
> Assisted-by: Azure:gtp-4.1-nano-key
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
>
> ----
>
> Changes in v16:
> - New commit
> ---
> drivers/acpi/apei/ghes.c | 6 +++++-
> drivers/cxl/core/ras.c | 1 -
> drivers/pci/pcie/aer_cxl_vh.c | 9 ++++++++-
> 3 files changed, 13 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/acpi/apei/ghes.c b/drivers/acpi/apei/ghes.c
> index 8acd2742bb27..de935e0e1dcf 100644
> --- a/drivers/acpi/apei/ghes.c
> +++ b/drivers/acpi/apei/ghes.c
> @@ -776,8 +776,12 @@ int cxl_cper_unregister_prot_err_work(struct work_struct *work)
> if (cxl_cper_prot_err_work != work)
> return -EINVAL;
>
> - guard(spinlock)(&cxl_cper_prot_err_work_lock);
> + spin_lock(&cxl_cper_prot_err_work_lock);
> cxl_cper_prot_err_work = NULL;
> + spin_unlock(&cxl_cper_prot_err_work_lock);
> +
> + cancel_work_sync(work);
> +
> return 0;
> }
> EXPORT_SYMBOL_NS_GPL(cxl_cper_unregister_prot_err_work, "CXL");
> diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c
> index 006c6ffc2f56..949d8c8ecdfe 100644
> --- a/drivers/cxl/core/ras.c
> +++ b/drivers/cxl/core/ras.c
> @@ -124,7 +124,6 @@ int cxl_ras_init(void)
> void cxl_ras_exit(void)
> {
> cxl_cper_unregister_prot_err_work(&cxl_cper_prot_err_work);
> - cancel_work_sync(&cxl_cper_prot_err_work);
> }
>
> static void cxl_dport_map_ras(struct cxl_dport *dport)
> diff --git a/drivers/pci/pcie/aer_cxl_vh.c b/drivers/pci/pcie/aer_cxl_vh.c
> index 7e2bc1894395..ebca1112652a 100644
> --- a/drivers/pci/pcie/aer_cxl_vh.c
> +++ b/drivers/pci/pcie/aer_cxl_vh.c
> @@ -74,8 +74,15 @@ EXPORT_SYMBOL_NS_GPL(cxl_register_proto_err_work, "CXL");
>
> void cxl_unregister_proto_err_work(void)
> {
> - guard(rwsem_write)(&cxl_proto_err_kfifo.rwsema);
> + struct work_struct *work;
> +
> + down_write(&cxl_proto_err_kfifo.rwsema);
> + work = cxl_proto_err_kfifo.work;
> cxl_proto_err_kfifo.work = NULL;
> + up_write(&cxl_proto_err_kfifo.rwsema);
> +
> + if (work)
> + cancel_work_sync(work);
> }
> EXPORT_SYMBOL_NS_GPL(cxl_unregister_proto_err_work, "CXL");
>
next prev parent reply other threads:[~2026-03-09 18:30 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-02 20:36 [PATCH v16 00/10] Enable CXL PCIe Port Protocol Error handling and logging Terry Bowman
2026-03-02 20:36 ` [PATCH v16 01/10] PCI/AER: Introduce AER-CXL Kfifo Terry Bowman
2026-03-09 12:20 ` Jonathan Cameron
2026-03-28 0:28 ` Dan Williams
2026-03-02 20:36 ` [PATCH v16 02/10] PCI/CXL: Update unregistration for AER-CXL and CPER-CXL kfifos Terry Bowman
2026-03-09 12:27 ` Jonathan Cameron
2026-03-11 15:03 ` Bowman, Terry
2026-03-09 18:30 ` Dave Jiang [this message]
2026-03-02 20:36 ` [PATCH v16 03/10] cxl: Update CXL Endpoint tracing Terry Bowman
2026-03-02 20:36 ` [PATCH v16 04/10] PCI/ERR: Introduce PCI_ERS_RESULT_PANIC Terry Bowman
2026-03-02 20:36 ` [PATCH v16 05/10] PCI: Establish common CXL Port protocol error flow Terry Bowman
2026-03-09 12:45 ` [PATCH v16 05/10] PCI: Establish common CXL Port protocol error flowUIRE Jonathan Cameron
2026-03-02 20:36 ` [PATCH v16 06/10] PCI/CXL: Add RCH support to CXL handlers Terry Bowman
2026-03-09 14:00 ` Jonathan Cameron
2026-03-11 15:21 ` Bowman, Terry
2026-03-02 20:36 ` [PATCH v16 07/10] cxl: Update error handlers to support CXL Port devices Terry Bowman
2026-03-09 14:05 ` Jonathan Cameron
2026-03-11 15:37 ` Bowman, Terry
2026-03-12 13:05 ` Jonathan Cameron
2026-03-02 20:36 ` [PATCH v16 08/10] cxl: Update Endpoint AER uncorrectable handler Terry Bowman
2026-03-09 14:12 ` Jonathan Cameron
2026-03-11 15:58 ` Bowman, Terry
2026-03-02 20:36 ` [PATCH v16 09/10] cxl: Remove Endpoint AER correctable handler Terry Bowman
2026-03-09 14:13 ` Jonathan Cameron
2026-03-09 18:55 ` Dave Jiang
2026-03-02 20:36 ` [PATCH v16 10/10] cxl: Enable CXL protocol error reporting Terry Bowman
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