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[2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-55f35c99ff5sm1666507e87.117.2025.08.25.09.37.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Aug 2025 09:37:01 -0700 (PDT) Date: Mon, 25 Aug 2025 19:36:59 +0300 From: Dmitry Baryshkov To: Luca Weiss Cc: Konrad Dybcio , Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Rafael J. Wysocki" , Viresh Kumar , Manivannan Sadhasivam , Herbert Xu , "David S. Miller" , Vinod Koul , Bjorn Andersson , Konrad Dybcio , Robert Marko , Das Srinagesh , Thomas Gleixner , Jassi Brar , Amit Kucheria , Thara Gopinath , Daniel Lezcano , Zhang Rui , Lukasz Luba , Ulf Hansson , ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-crypto@vger.kernel.org, dmaengine@vger.kernel.org, linux-mmc@vger.kernel.org Subject: Re: [PATCH v2 14/15] arm64: dts: qcom: Add initial Milos dtsi Message-ID: <2bk7s43nrkmhhgsqq65mxhbmrapyjejyjugnae7wfbttqjmtbf@dk2fe64qrmwx> References: <20250713-sm7635-fp6-initial-v2-0-e8f9a789505b@fairphone.com> <20250713-sm7635-fp6-initial-v2-14-e8f9a789505b@fairphone.com> <3e0299ad-766a-4876-912e-438fe2cc856d@oss.qualcomm.com> <55420d89-fcd4-4cb5-a918-d8bbe2a03d19@oss.qualcomm.com> <2hv4yuc7rgtglihc2um2lr5ix4dfqxd4abb2bqb445zkhpjpsi@rozikfwrdtlk> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Proofpoint-GUID: OociW_rVELTAdj2UZlqMHtZBgK8oCyNB X-Proofpoint-ORIG-GUID: OociW_rVELTAdj2UZlqMHtZBgK8oCyNB X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODIzMDAzMyBTYWx0ZWRfX9NhCECUuGXSZ WHVlMvXHBD6q6HdzgUYjC6WKvZBXuKXVgTyrumHj+bLja03R1WnLlXosl4IOSH34CAflebcwm7q 9ae6IctE5c0PEdwwCP27Fu9vxUi8i1xPDOhSwnVa2cY810cS21gSyyZ74LDYfmpY6xg45uYHueC xUruPdI7tg/VABxH2Th+5W4W9q7exJ6c3wVYU+jTwvErBmUiMqCppVuzbkMtoaR5lYQwsheYDWC va7mTYRewkgsG0xHgu/G86eW/6ps6b7Qp++XZxntIIZh1GnDhhicSJa6zpRSqGXybVuoedoyPfg Gg28N/EED/pxmvORzgpXGuhk/rmReixtTY3apOiltb0oMV/pl82cU7BmnV8ekTt7kK6Uk4iNB5a EvDhXJKj X-Authority-Analysis: v=2.4 cv=BJazrEQG c=1 sm=1 tr=0 ts=68ac9130 cx=c_pps a=mPf7EqFMSY9/WdsSgAYMbA==:117 a=xqWC_Br6kY4A:10 a=kj9zAlcOel0A:10 a=2OwXVqhp2XgA:10 a=6H0WHjuAAAAA:8 a=HmU3_siD3n1fRUalNNUA:9 a=CjuIK1q_8ugA:10 a=dawVfQjAaf238kedN5IG:22 a=Soq9LBFxuPC4vsCAQt-j:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-25_08,2025-08-20_03,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 priorityscore=1501 clxscore=1015 impostorscore=0 bulkscore=0 phishscore=0 suspectscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508230033 On Mon, Aug 25, 2025 at 05:53:53PM +0200, Luca Weiss wrote: > Hi Dmitry, > > On Wed Aug 20, 2025 at 1:52 PM CEST, Dmitry Baryshkov wrote: > > On Wed, Aug 20, 2025 at 10:42:09AM +0200, Luca Weiss wrote: > >> Hi Konrad, > >> > >> On Sat Aug 2, 2025 at 2:04 PM CEST, Konrad Dybcio wrote: > >> > On 7/29/25 8:49 AM, Luca Weiss wrote: > >> >> Hi Konrad, > >> >> > >> >> On Thu Jul 17, 2025 at 11:46 AM CEST, Luca Weiss wrote: > >> >>> Hi Konrad, > >> >>> > >> >>> On Thu Jul 17, 2025 at 10:29 AM CEST, Luca Weiss wrote: > >> >>>> On Mon Jul 14, 2025 at 1:06 PM CEST, Konrad Dybcio wrote: > >> >>>>> On 7/13/25 10:05 AM, Luca Weiss wrote: > >> >>>>>> Add a devicetree description for the Milos SoC, which is for example > >> >>>>>> Snapdragon 7s Gen 3 (SM7635). > >> >>>>>> > >> >>>>>> Signed-off-by: Luca Weiss > >> >>>>>> --- > >> >>>>> > >> >>>>> [...] > >> >>>>>> + > >> >>>>>> + spmi_bus: spmi@c400000 { > >> >>>>>> + compatible = "qcom,spmi-pmic-arb"; > >> >>>>> > >> >>>>> There's two bus instances on this platform, check out the x1e binding > >> >>>> > >> >>>> Will do > >> >>> > >> >>> One problem: If we make the labels spmi_bus0 and spmi_bus1 then we can't > >> >>> reuse the existing PMIC dtsi files since they all reference &spmi_bus. > >> >>> > >> >>> On FP6 everything's connected to PMIC_SPMI0_*, and PMIC_SPMI1_* is not > >> >>> connected to anything so just adding the label spmi_bus on spmi_bus0 > >> >>> would be fine. > >> >>> > >> >>> Can I add this to the device dts? Not going to be pretty though... > >> >>> > >> >>> diff --git a/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts b/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts > >> >>> index d12eaa585b31..69605c9ed344 100644 > >> >>> --- a/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts > >> >>> +++ b/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts > >> >>> @@ -11,6 +11,9 @@ > >> >>> #include > >> >>> #include > >> >>> #include "milos.dtsi" > >> >>> + > >> >>> +spmi_bus: &spmi_bus0 {}; > >> >>> + > >> >>> #include "pm7550.dtsi" > >> >>> #include "pm8550vs.dtsi" > >> >>> #include "pmiv0104.dtsi" /* PMIV0108 */ > >> >>> > >> >>> Or I can add a second label for the spmi_bus0 as 'spmi_bus'. Not sure > >> >>> other designs than SM7635 recommend using spmi_bus1 for some stuff. > >> >>> > >> >>> But I guess longer term we'd need to figure out a solution to this, how > >> >>> to place a PMIC on a given SPMI bus, if reference designs start to > >> >>> recommend putting different PMIC on the separate busses. > >> >> > >> >> Any feedback on this regarding the spmi_bus label? > >> > > >> > I had an offline chat with Bjorn and we only came up with janky > >> > solutions :) > >> > > >> > What you propose works well if the PMICs are all on bus0, which is > >> > not the case for the newest platforms. If some instances are on bus0 > >> > and others are on bus1, things get ugly really quick and we're going > >> > to drown in #ifdefs. > >> > > >> > > >> > An alternative that I've seen downstream is to define PMIC nodes in > >> > the root of a dtsi file (not in the root of DT, i.e. NOT under / { }) > >> > and do the following: > >> > > >> > &spmi_busN { > >> > #include "pmABCDX.dtsi" > >> > }; > >> > > >> > Which is "okay", but has the visible downside of having to define the > >> > temp alarm thermal zone in each board's DT separately (and doing > >> > mid-file includes which is.. fine I guess, but also something we avoided > >> > upstream for the longest time) > >> > > >> > > >> > Both are less than ideal when it comes to altering the SID under > >> > "interrupts", fixing that would help immensely. We were hoping to > >> > leverage something like Johan's work on drivers/mfd/qcom-pm8008.c, > >> > but that seems like a longer term project. > >> > > >> > Please voice your opinions > >> > >> Since nobody else jumped in, how can we continue? > >> > >> One janky solution in my mind is somewhat similar to the PMxxxx_SID > >> defines, doing something like "#define PM7550_SPMI spmi_bus0" and then > >> using "&PM7550_SPMI {}" in the dtsi. I didn't try it so not sure that > >> actually works but something like this should I imagine. > >> > >> But fortunately my Milos device doesn't have the problem that it > >> actually uses both SPMI busses for different PMICs, so similar to other > >> SoCs that already have two SPMI busses, I could somewhat ignore the > >> problem and let someone else figure out how to actually place PMICs on > >> spmi_bus0 and spmi_bus1 if they have such a hardware. > > > > I'd say, ignore it for now. > > You mean ignoring that there's a second SPMI bus on this SoC, and just > modelling one with the label "spmi_bus"? Or something else? > > > I have also actually tried out the C define solution that I was writing > about in my previous email and this is actually working, see diff below. > In my opinion it just expands on what we have with the SID defines, so > shouldn't be tooo unacceptable :) I think we tried previously using C preprocessor to rework SID handling and it wasn't accepted by DT maintainers. I'd say, ignore the second bus for now, unless it gets actually used for major PMICs. -- With best wishes Dmitry