From: Stephen Boyd <sboyd@kernel.org>
To: bigunclemax@gmail.com
Cc: bigunclemax@gmail.com, Drew Fustini <drew@pdp7.com>,
Guo Ren <guoren@kernel.org>, Fu Wei <wefu@redhat.com>,
Michael Turquette <mturquette@baylibre.com>,
Yangtao Li <frank.li@vivo.com>,
Jisheng Zhang <jszhang@kernel.org>,
linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2] clk: thead: Fix TH1520 emmc and shdci clock rate
Date: Tue, 17 Dec 2024 12:18:15 -0800 [thread overview]
Message-ID: <2c0e701d9fcf69090daf8c4087c87d2a.sboyd@kernel.org> (raw)
In-Reply-To: <20241210083029.92620-1-bigunclemax@gmail.com>
Quoting bigunclemax@gmail.com (2024-12-10 00:30:27)
> From: Maksim Kiselev <bigunclemax@gmail.com>
>
> In accordance with LicheePi 4A BSP the clock that comes to emmc/sdhci
> is 198Mhz which is got through frequency division of source clock
> VIDEO PLL by 4 [1].
>
> But now the AP_SUBSYS driver sets the CLK EMMC SDIO to the same
> frequency as the VIDEO PLL, equal to 792 MHz. This causes emmc/sdhci
> to work 4 times slower.
>
> Let's fix this issue by adding fixed factor clock that divides
> VIDEO PLL by 4 for emmc/sdhci.
>
> Link: https://github.com/revyos/thead-kernel/blob/7563179071a314f41cdcdbfd8cf6e101e73707f3/drivers/clk/thead/clk-light-fm.c#L454
>
> Fixes: ae81b69fd2b1 ("clk: thead: Add support for T-Head TH1520 AP_SUBSYS clocks")
> Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com>
> ---
Applied to clk-fixes
next prev parent reply other threads:[~2024-12-17 20:18 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-12-10 8:30 [PATCH v2] clk: thead: Fix TH1520 emmc and shdci clock rate bigunclemax
2024-12-10 10:07 ` Xi Ruoyao
2024-12-11 16:59 ` Drew Fustini
2024-12-17 20:18 ` Stephen Boyd [this message]
2025-02-03 19:16 ` patchwork-bot+linux-riscv
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