* [PATCH 0/3] MT8189 IOMMU SUPPORT
@ 2025-08-07 9:57 zhengnan chen
2025-08-07 9:57 ` [PATCH 1/3] dt-bindings: mediatek: mt8189: Add bindings for MM & APU & INFRA IOMMU zhengnan chen
` (2 more replies)
0 siblings, 3 replies; 9+ messages in thread
From: zhengnan chen @ 2025-08-07 9:57 UTC (permalink / raw)
To: Yong Wu, Joerg Roedel, Will Deacon, Robin Murphy, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno
Cc: iommu, linux-mediatek, devicetree, linux-kernel, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group, zhengnan chen
Based on tag: next-20250806, linux-next/master
This patchset adds MT8189 iommu support.
MT8189 have 3 IOMMU HWs. 1 IOMMU HW is for multimedia,
1 IOMMU HW is for apu(AI processer unit),
and 2 IOMMU HW is for infra-master, like PCIe/USB.
About the INFRA IOMMU, it don't have larbs, the master connects the
iommu directly. It use a independent pgtable, and these two
INFRA IOMMU HW share a pgtable.
In mt8189, the display connect with larb1 and larb2 at the same time.
Thus, we should add link between disp-dev with these two larbs.
The software solutions can be summarized as follows:
1. Add iommu support for mt8189
2. Add a flag DL_WITH_MULTI_LARB to support the HW which connect with
multiple larbs.
zhengnan.chen (3):
dt-bindings: mediatek: mt8189: Add bindings for MM & APU & INFRA IOMMU
iommu/mediatek: Add a flag DL_WITH_MULTI_LARB
iommu/mediatek: Add support for mt8189
.../bindings/iommu/mediatek,iommu.yaml | 7 +
drivers/iommu/mtk_iommu.c | 132 +++++++-
.../memory/mediatek,mt8189-memory-port.h | 283 ++++++++++++++++++
3 files changed, 409 insertions(+), 13 deletions(-)
create mode 100644 include/dt-bindings/memory/mediatek,mt8189-memory-port.h
--
2.46.0
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH 1/3] dt-bindings: mediatek: mt8189: Add bindings for MM & APU & INFRA IOMMU 2025-08-07 9:57 [PATCH 0/3] MT8189 IOMMU SUPPORT zhengnan chen @ 2025-08-07 9:57 ` zhengnan chen 2025-08-07 15:23 ` Matthias Brugger 2025-08-07 16:12 ` Conor Dooley 2025-08-07 9:57 ` [PATCH 2/3] iommu/mediatek: Add a flag DL_WITH_MULTI_LARB zhengnan chen 2025-08-07 9:57 ` [PATCH 3/3] iommu/mediatek: Add support for mt8189 zhengnan chen 2 siblings, 2 replies; 9+ messages in thread From: zhengnan chen @ 2025-08-07 9:57 UTC (permalink / raw) To: Yong Wu, Joerg Roedel, Will Deacon, Robin Murphy, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno Cc: iommu, linux-mediatek, devicetree, linux-kernel, linux-arm-kernel, Project_Global_Chrome_Upstream_Group, zhengnan chen From: "zhengnan chen" <zhengnan.chen@mediatek.com> There are three iommu in total, namely MM_IOMMU, APU_IOMMU, INFRA_IOMMU, Add bindings for them. Signed-off-by: zhengnan chen <zhengnan.chen@mediatek.com> --- .../bindings/iommu/mediatek,iommu.yaml | 7 + .../memory/mediatek,mt8189-memory-port.h | 283 ++++++++++++++++++ 2 files changed, 290 insertions(+) create mode 100644 include/dt-bindings/memory/mediatek,mt8189-memory-port.h diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml index 75750c64157c..32ca618c08dc 100644 --- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml +++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml @@ -82,6 +82,9 @@ properties: - mediatek,mt8188-iommu-vdo # generation two - mediatek,mt8188-iommu-vpp # generation two - mediatek,mt8188-iommu-infra # generation two + - mediatek,mt8189-iommu-apu # generation two + - mediatek,mt8189-iommu-infra # generation two + - mediatek,mt8189-iommu-mm # generation two - mediatek,mt8192-m4u # generation two - mediatek,mt8195-iommu-vdo # generation two - mediatek,mt8195-iommu-vpp # generation two @@ -128,6 +131,7 @@ properties: This is the mtk_m4u_id according to the HW. Specifies the mtk_m4u_id as defined in dt-binding/memory/mediatek,mt8188-memory-port.h for mt8188, + dt-binding/memory/mediatek,mt8189-memory-port.h for mt8189, dt-binding/memory/mt2701-larb-port.h for mt2701 and mt7623, dt-binding/memory/mt2712-larb-port.h for mt2712, dt-binding/memory/mt6779-larb-port.h for mt6779, @@ -164,6 +168,7 @@ allOf: - mediatek,mt8186-iommu-mm - mediatek,mt8188-iommu-vdo - mediatek,mt8188-iommu-vpp + - mediatek,mt8189-iommu-mm - mediatek,mt8192-m4u - mediatek,mt8195-iommu-vdo - mediatek,mt8195-iommu-vpp @@ -180,6 +185,7 @@ allOf: - mediatek,mt8186-iommu-mm - mediatek,mt8188-iommu-vdo - mediatek,mt8188-iommu-vpp + - mediatek,mt8189-iommu-mm - mediatek,mt8192-m4u - mediatek,mt8195-iommu-vdo - mediatek,mt8195-iommu-vpp @@ -208,6 +214,7 @@ allOf: contains: enum: - mediatek,mt8188-iommu-infra + - mediatek,mt8189-iommu-infra - mediatek,mt8195-iommu-infra then: diff --git a/include/dt-bindings/memory/mediatek,mt8189-memory-port.h b/include/dt-bindings/memory/mediatek,mt8189-memory-port.h new file mode 100644 index 000000000000..849fead3d0f7 --- /dev/null +++ b/include/dt-bindings/memory/mediatek,mt8189-memory-port.h @@ -0,0 +1,283 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2025 MediaTek Inc. + * Author: Zhengnan chen <zhengnan.chen@mediatek.com> + */ +#ifndef _DT_BINDINGS_MEMORY_MEDIATEK_MT8189_MEMORY_PORT_H_ +#define _DT_BINDINGS_MEMORY_MEDIATEK_MT8189_MEMORY_PORT_H_ + +#include <dt-bindings/memory/mtk-memory-port.h> + +#define SMI_L0_ID (0) +#define SMI_L1_ID (1) +#define SMI_L2_ID (2) +#define SMI_L4_ID (3) +#define SMI_L7_ID (4) +#define SMI_L9_ID (5) +#define SMI_L11_ID (6) +#define SMI_L13_ID (7) +#define SMI_L14_ID (8) +#define SMI_L16_ID (9) +#define SMI_L17_ID (10) +#define SMI_L19_ID (11) +#define SMI_L20_ID (12) + +/* + * MM IOMMU supports 16GB dma address. We separate it to four ranges: + * 0 ~ 4G; 4G ~ 8G; 8G ~ 12G; 12G ~ 16G, we could adjust these masters + * locate in anyone region. BUT: + * a) Make sure all the ports inside a larb are in one range. + * b) The iova of any master can NOT cross the 4G/8G/12G boundary. + * + * This is the suggested mapping in this SoC: + * + * modules dma-address-region larbs-ports + * disp/mdp 0 ~ 4G larb0/1/2 + * vcodec 4G ~ 8G larb4/7 + * imgsys/cam/ipesys 8G ~ 12G the other larbs. + * N/A 12G ~ 16G + */ + +/* Larb0 -- disp */ +#define M4U_L0_P0_DISP_OVL0_4L_HDR MTK_M4U_ID(SMI_L0_ID, 0) +#define M4U_L0_P1_DISP_OVL0_4L_RDMA0 MTK_M4U_ID(SMI_L0_ID, 1) +#define M4U_L0_P2_DISP_OVL1_4L_RDMA1 MTK_M4U_ID(SMI_L0_ID, 2) +#define M4U_L0_P3_DISP_OVL0_4L_RDMA2 MTK_M4U_ID(SMI_L0_ID, 3) +#define M4U_L0_P4_DISP_OVL1_4L_RDMA3 MTK_M4U_ID(SMI_L0_ID, 4) +#define M4U_L0_P5_DISP_RDMA0 MTK_M4U_ID(SMI_L0_ID, 5) +#define M4U_L0_P6_DISP_WDMA0 MTK_M4U_ID(SMI_L0_ID, 6) +#define M4U_L0_P7_DISP_FAKE_ENG0 MTK_M4U_ID(SMI_L0_ID, 7) + +/* Larb1 -- disp */ +#define M4U_L1_P0_DISP_OVL1_4L_HDR MTK_M4U_ID(SMI_L1_ID, 0) +#define M4U_L1_P1_DISP_OVL1_4L_RDMA0 MTK_M4U_ID(SMI_L1_ID, 1) +#define M4U_L1_P2_DISP_OVL0_4L_RDMA1 MTK_M4U_ID(SMI_L1_ID, 2) +#define M4U_L1_P3_DISP_OVL1_4L_RDMA2 MTK_M4U_ID(SMI_L1_ID, 3) +#define M4U_L1_P4_DISP_OVL0_4L_RDMA3 MTK_M4U_ID(SMI_L1_ID, 4) +#define M4U_L1_P5_DISP_RDMA1 MTK_M4U_ID(SMI_L1_ID, 5) +#define M4U_L1_P6_DISP_WDMA1 MTK_M4U_ID(SMI_L1_ID, 6) +#define M4U_L1_P7_DISP_FAKE_ENG1 MTK_M4U_ID(SMI_L1_ID, 7) + +/* Larb2 -- mmlsys(mdp) */ +#define M4U_L2_P0_MDP_RDMA0 MTK_M4U_ID(SMI_L2_ID, 0) +#define M4U_L2_P1_MDP_RDMA1 MTK_M4U_ID(SMI_L2_ID, 1) +#define M4U_L2_P2_MDP_WROT0 MTK_M4U_ID(SMI_L2_ID, 2) +#define M4U_L2_P3_MDP_WROT1 MTK_M4U_ID(SMI_L2_ID, 3) +#define M4U_L2_P4_MDP_DUMMY0 MTK_M4U_ID(SMI_L2_ID, 4) +#define M4U_L2_P5_MDP_DUMMY1 MTK_M4U_ID(SMI_L2_ID, 5) +#define M4U_L2_P6_MDP_RDMA2 MTK_M4U_ID(SMI_L2_ID, 6) +#define M4U_L2_P7_MDP_RDMA3 MTK_M4U_ID(SMI_L2_ID, 7) +#define M4U_L2_P8_MDP_WROT2 MTK_M4U_ID(SMI_L2_ID, 8) +#define M4U_L2_P9_MDP_WROT3 MTK_M4U_ID(SMI_L2_ID, 9) +#define M4U_L2_P10_DISP_FAKE0 MTK_M4U_ID(SMI_L2_ID, 10) + +/* Larb3: null */ + +/* Larb4 -- vdec */ +#define M4U_L4_P0_HW_VDEC_MC_EXT MTK_M4U_ID(SMI_L4_ID, 0) +#define M4U_L4_P1_HW_VDEC_UFO_EXT MTK_M4U_ID(SMI_L4_ID, 1) +#define M4U_L4_P2_HW_VDEC_PP_EXT MTK_M4U_ID(SMI_L4_ID, 2) +#define M4U_L4_P3_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(SMI_L4_ID, 3) +#define M4U_L4_P4_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(SMI_L4_ID, 4) +#define M4U_L4_P5_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(SMI_L4_ID, 5) +#define M4U_L4_P6_HW_VDEC_TILE_EXT MTK_M4U_ID(SMI_L4_ID, 6) +#define M4U_L4_P7_HW_VDEC_VLD_EXT MTK_M4U_ID(SMI_L4_ID, 7) +#define M4U_L4_P8_HW_VDEC_VLD2_EXT MTK_M4U_ID(SMI_L4_ID, 8) +#define M4U_L4_P9_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(SMI_L4_ID, 9) +#define M4U_L4_P10_HW_VDEC_RG_CTRL_DMA_EXT MTK_M4U_ID(SMI_L4_ID, 10) +#define M4U_L4_P11_HW_VDEC_UFO_ENC_EXT MTK_M4U_ID(SMI_L4_ID, 11) + +/* Larb5: null */ + +/* Larb6: null */ + +/* Larb7 -- venc */ +#define M4U_L7_P0_VENC_RCPU MTK_M4U_ID(SMI_L7_ID, 0) +#define M4U_L7_P1_VENC_REC MTK_M4U_ID(SMI_L7_ID, 1) +#define M4U_L7_P2_VENC_BSDMA MTK_M4U_ID(SMI_L7_ID, 2) +#define M4U_L7_P3_VENC_SV_COMV MTK_M4U_ID(SMI_L7_ID, 3) +#define M4U_L7_P4_VENC_RD_COMV MTK_M4U_ID(SMI_L7_ID, 4) +#define M4U_L7_P5_JPGENC_Y_RDMA MTK_M4U_ID(SMI_L7_ID, 5) +#define M4U_L7_P6_JPGENC_C_RDMA MTK_M4U_ID(SMI_L7_ID, 6) +#define M4U_L7_P7_JPGENC_Q_RDMA MTK_M4U_ID(SMI_L7_ID, 7) +#define M4U_L7_P8_VENC_SUB_W_LUMA MTK_M4U_ID(SMI_L7_ID, 8) +#define M4U_L7_P9_JPGENC_BSDMA MTK_M4U_ID(SMI_L7_ID, 9) +#define M4U_L7_P10_VENC_CUR_LUMA MTK_M4U_ID(SMI_L7_ID, 10) +#define M4U_L7_P11_VENC_CUR_CHROMA MTK_M4U_ID(SMI_L7_ID, 11) +#define M4U_L7_P12_VENC_REF_LUMA MTK_M4U_ID(SMI_L7_ID, 12) +#define M4U_L7_P13_VENC_REF_CHROMA MTK_M4U_ID(SMI_L7_ID, 13) +#define M4U_L7_P14_VENC_SUB_R_LUMA MTK_M4U_ID(SMI_L7_ID, 14) +#define M4U_L7_P15_JPGDEC_WDMA MTK_M4U_ID(SMI_L7_ID, 15) +#define M4U_L7_P16_JPGDEC_BSDMA MTK_M4U_ID(SMI_L7_ID, 16) +#define M4U_L7_P17_JPGDEC_HUFF_OFFSET MTK_M4U_ID(SMI_L7_ID, 17) + +/* Larb8: null */ + +/* Larb9 --imgsys */ +#define M4U_L9_P0_IMGI_D1 MTK_M4U_ID(SMI_L9_ID, 0) +#define M4U_L9_P1_IMGBI_D1 MTK_M4U_ID(SMI_L9_ID, 1) +#define M4U_L9_P2_DMGI_D1 MTK_M4U_ID(SMI_L9_ID, 2) +#define M4U_L9_P3_DEPI_D1 MTK_M4U_ID(SMI_L9_ID, 3) +#define M4U_L9_P4_LCE_D1 MTK_M4U_ID(SMI_L9_ID, 4) +#define M4U_L9_P5_SMTI_D1 MTK_M4U_ID(SMI_L9_ID, 5) +#define M4U_L9_P6_SMTO_D2 MTK_M4U_ID(SMI_L9_ID, 6) +#define M4U_L9_P7_SMTO_D1 MTK_M4U_ID(SMI_L9_ID, 7) +#define M4U_L9_P8_CRZO_D1 MTK_M4U_ID(SMI_L9_ID, 8) +#define M4U_L9_P9_IMG3O_D1 MTK_M4U_ID(SMI_L9_ID, 9) +#define M4U_L9_P10_VIPI_D1 MTK_M4U_ID(SMI_L9_ID, 10) +#define M4U_L9_P11_SMTI_D5 MTK_M4U_ID(SMI_L9_ID, 11) +#define M4U_L9_P12_TIMGO_D1 MTK_M4U_ID(SMI_L9_ID, 12) +#define M4U_L9_P13_UFBC_W0 MTK_M4U_ID(SMI_L9_ID, 13) +#define M4U_L9_P14_UFBC_R0 MTK_M4U_ID(SMI_L9_ID, 14) +#define M4U_L9_P15_WPE_RDMA1 MTK_M4U_ID(SMI_L9_ID, 15) +#define M4U_L9_P16_WPE_RDMA0 MTK_M4U_ID(SMI_L9_ID, 16) +#define M4U_L9_P17_WPE_WDMA MTK_M4U_ID(SMI_L9_ID, 17) +#define M4U_L9_P18_MFB_RDMA0 MTK_M4U_ID(SMI_L9_ID, 18) +#define M4U_L9_P19_MFB_RDMA1 MTK_M4U_ID(SMI_L9_ID, 19) +#define M4U_L9_P20_MFB_RDMA2 MTK_M4U_ID(SMI_L9_ID, 20) +#define M4U_L9_P21_MFB_RDMA3 MTK_M4U_ID(SMI_L9_ID, 21) +#define M4U_L9_P22_MFB_RDMA4 MTK_M4U_ID(SMI_L9_ID, 22) +#define M4U_L9_P23_MFB_RDMA5 MTK_M4U_ID(SMI_L9_ID, 23) +#define M4U_L9_P24_MFB_WDMA0 MTK_M4U_ID(SMI_L9_ID, 24) +#define M4U_L9_P25_MFB_WDMA1 MTK_M4U_ID(SMI_L9_ID, 25) +#define M4U_L9_P26_RESERVE6 MTK_M4U_ID(SMI_L9_ID, 26) +#define M4U_L9_P27_RESERVE7 MTK_M4U_ID(SMI_L9_ID, 27) +#define M4U_L9_P28_RESERVE8 MTK_M4U_ID(SMI_L9_ID, 28) + +/* Larb10: null */ + +/* Larb11 -- imgsys */ +#define M4U_L11_P0_IMGI_D1 MTK_M4U_ID(SMI_L11_ID, 0) +#define M4U_L11_P1_IMGBI_D1 MTK_M4U_ID(SMI_L11_ID, 1) +#define M4U_L11_P2_DMGI_D1 MTK_M4U_ID(SMI_L11_ID, 2) +#define M4U_L11_P3_DEPI_D1 MTK_M4U_ID(SMI_L11_ID, 3) +#define M4U_L11_P4_LCE_D1 MTK_M4U_ID(SMI_L11_ID, 4) +#define M4U_L11_P5_SMTI_D1 MTK_M4U_ID(SMI_L11_ID, 5) +#define M4U_L11_P6_SMTO_D2 MTK_M4U_ID(SMI_L11_ID, 6) +#define M4U_L11_P7_SMTO_D1 MTK_M4U_ID(SMI_L11_ID, 7) +#define M4U_L11_P8_CRZO_D1 MTK_M4U_ID(SMI_L11_ID, 8) +#define M4U_L11_P9_IMG3O_D1 MTK_M4U_ID(SMI_L11_ID, 9) +#define M4U_L11_P10_VIPI_D1 MTK_M4U_ID(SMI_L11_ID, 10) +#define M4U_L11_P11_SMTI_D5 MTK_M4U_ID(SMI_L11_ID, 11) +#define M4U_L11_P12_TIMGO_D1 MTK_M4U_ID(SMI_L11_ID, 12) +#define M4U_L11_P13_UFBC_W0 MTK_M4U_ID(SMI_L11_ID, 13) +#define M4U_L11_P14_UFBC_R0 MTK_M4U_ID(SMI_L11_ID, 14) +#define M4U_L11_P15_WPE_RDMA1 MTK_M4U_ID(SMI_L11_ID, 15) +#define M4U_L11_P16_WPE_RDMA0 MTK_M4U_ID(SMI_L11_ID, 16) +#define M4U_L11_P17_WPE_WDMA MTK_M4U_ID(SMI_L11_ID, 17) +#define M4U_L11_P18_MFB_RDMA0 MTK_M4U_ID(SMI_L11_ID, 18) +#define M4U_L11_P19_MFB_RDMA1 MTK_M4U_ID(SMI_L11_ID, 19) +#define M4U_L11_P20_MFB_RDMA2 MTK_M4U_ID(SMI_L11_ID, 20) +#define M4U_L11_P21_MFB_RDMA3 MTK_M4U_ID(SMI_L11_ID, 21) +#define M4U_L11_P22_MFB_RDMA4 MTK_M4U_ID(SMI_L11_ID, 22) +#define M4U_L11_P23_MFB_RDMA5 MTK_M4U_ID(SMI_L11_ID, 23) +#define M4U_L11_P24_MFB_WDMA0 MTK_M4U_ID(SMI_L11_ID, 24) +#define M4U_L11_P25_MFB_WDMA1 MTK_M4U_ID(SMI_L11_ID, 25) +#define M4U_L11_P26_RESERVE6 MTK_M4U_ID(SMI_L11_ID, 26) +#define M4U_L11_P27_RESERVE7 MTK_M4U_ID(SMI_L11_ID, 27) +#define M4U_L11_P28_RESERVE8 MTK_M4U_ID(SMI_L11_ID, 28) + +/* Larb12: null */ + +/* Larb13 -- cam */ +#define M4U_L13_P0_MRAWI MTK_M4U_ID(SMI_L13_ID, 0) +#define M4U_L13_P1_MRAWO_0 MTK_M4U_ID(SMI_L13_ID, 1) +#define M4U_L13_P2_MRAWO_1 MTK_M4U_ID(SMI_L13_ID, 2) +#define M4U_L13_P3_CAMSV_1 MTK_M4U_ID(SMI_L13_ID, 3) +#define M4U_L13_P4_CAMSV_2 MTK_M4U_ID(SMI_L13_ID, 4) +#define M4U_L13_P5_CAMSV_3 MTK_M4U_ID(SMI_L13_ID, 5) +#define M4U_L13_P6_CAMSV_4 MTK_M4U_ID(SMI_L13_ID, 6) +#define M4U_L13_P7_CAMSV_5 MTK_M4U_ID(SMI_L13_ID, 7) +#define M4U_L13_P8_CAMSV_6 MTK_M4U_ID(SMI_L13_ID, 8) +#define M4U_L13_P9_CCUI MTK_M4U_ID(SMI_L13_ID, 9) +#define M4U_L13_P10_CCUO MTK_M4U_ID(SMI_L13_ID, 10) +#define M4U_L13_P11_FAKE MTK_M4U_ID(SMI_L13_ID, 11) +#define M4U_L13_P12_PDAI_0 MTK_M4U_ID(SMI_L13_ID, 12) +#define M4U_L13_P13_PDAI_1 MTK_M4U_ID(SMI_L13_ID, 13) +#define M4U_L13_P14_PDAO MTK_M4U_ID(SMI_L13_ID, 14) + +/* Larb14 -- cam */ +#define M4U_L14_P0_RESERVE MTK_M4U_ID(SMI_L14_ID, 0) +#define M4U_L14_P1_RESERVE MTK_M4U_ID(SMI_L14_ID, 1) +#define M4U_L14_P2_RESERVE MTK_M4U_ID(SMI_L14_ID, 2) +#define M4U_L14_P3_CAMSV_0 MTK_M4U_ID(SMI_L14_ID, 3) +#define M4U_L14_P4_CCUI MTK_M4U_ID(SMI_L14_ID, 4) +#define M4U_L14_P5_CCUO MTK_M4U_ID(SMI_L14_ID, 5) +#define M4U_L14_P6_CAMSV_7 MTK_M4U_ID(SMI_L14_ID, 6) +#define M4U_L14_P7_CAMSV_8 MTK_M4U_ID(SMI_L14_ID, 7) +#define M4U_L14_P8_CAMSV_9 MTK_M4U_ID(SMI_L14_ID, 8) +#define M4U_L14_P9_CAMSV_10 MTK_M4U_ID(SMI_L14_ID, 9) + +/* Larb15: null */ + +/* Larb16 -- cam */ +#define M4U_L16_P0_IMGO_R1_A MTK_M4U_ID(SMI_L16_ID, 0) +#define M4U_L16_P1_RRZO_R1_A MTK_M4U_ID(SMI_L16_ID, 1) +#define M4U_L16_P2_CQI_R1_A MTK_M4U_ID(SMI_L16_ID, 2) +#define M4U_L16_P3_BPCI_R1_A MTK_M4U_ID(SMI_L16_ID, 3) +#define M4U_L16_P4_YUVO_R1_A MTK_M4U_ID(SMI_L16_ID, 4) +#define M4U_L16_P5_UFDI_R2_A MTK_M4U_ID(SMI_L16_ID, 5) +#define M4U_L16_P6_RAWI_R2_A MTK_M4U_ID(SMI_L16_ID, 6) +#define M4U_L16_P7_RAWI_R3_A MTK_M4U_ID(SMI_L16_ID, 7) +#define M4U_L16_P8_AAO_R1_A MTK_M4U_ID(SMI_L16_ID, 8) +#define M4U_L16_P9_AFO_R1_A MTK_M4U_ID(SMI_L16_ID, 9) +#define M4U_L16_P10_FLKO_R1_A MTK_M4U_ID(SMI_L16_ID, 10) +#define M4U_L16_P11_LCESO_R1_A MTK_M4U_ID(SMI_L16_ID, 11) +#define M4U_L16_P12_CRZO_R1_A MTK_M4U_ID(SMI_L16_ID, 12) +#define M4U_L16_P13_LTMSO_R1_A MTK_M4U_ID(SMI_L16_ID, 13) +#define M4U_L16_P14_RSSO_R1_A MTK_M4U_ID(SMI_L16_ID, 14) +#define M4U_L16_P15_AAHO_R1_A MTK_M4U_ID(SMI_L16_ID, 15) +#define M4U_L16_P16_LSCI_R1_A MTK_M4U_ID(SMI_L16_ID, 16) + +/* Larb17 -- cam */ +#define M4U_L17_P0_IMGO_R1_B MTK_M4U_ID(SMI_L17_ID, 0) +#define M4U_L17_P1_RRZO_R1_B MTK_M4U_ID(SMI_L17_ID, 1) +#define M4U_L17_P2_CQI_R1_B MTK_M4U_ID(SMI_L17_ID, 2) +#define M4U_L17_P3_BPCI_R1_B MTK_M4U_ID(SMI_L17_ID, 3) +#define M4U_L17_P4_YUVO_R1_B MTK_M4U_ID(SMI_L17_ID, 4) +#define M4U_L17_P5_UFDI_R2_B MTK_M4U_ID(SMI_L17_ID, 5) +#define M4U_L17_P6_RAWI_R2_B MTK_M4U_ID(SMI_L17_ID, 6) +#define M4U_L17_P7_RAWI_R3_B MTK_M4U_ID(SMI_L17_ID, 7) +#define M4U_L17_P8_AAO_R1_B MTK_M4U_ID(SMI_L17_ID, 8) +#define M4U_L17_P9_AFO_R1_B MTK_M4U_ID(SMI_L17_ID, 9) +#define M4U_L17_P10_FLKO_R1_B MTK_M4U_ID(SMI_L17_ID, 10) +#define M4U_L17_P11_LCESO_R1_B MTK_M4U_ID(SMI_L17_ID, 11) +#define M4U_L17_P12_CRZO_R1_B MTK_M4U_ID(SMI_L17_ID, 12) +#define M4U_L17_P13_LTMSO_R1_B MTK_M4U_ID(SMI_L17_ID, 13) +#define M4U_L17_P14_RSSO_R1_B MTK_M4U_ID(SMI_L17_ID, 14) +#define M4U_L17_P15_AAHO_R1_B MTK_M4U_ID(SMI_L17_ID, 15) +#define M4U_L17_P16_LSCI_R1_B MTK_M4U_ID(SMI_L17_ID, 16) + +/* Larb19 -- ipesys */ +#define M4U_L19_P0_DVS_RDMA MTK_M4U_ID(SMI_L19_ID, 0) +#define M4U_L19_P1_DVS_WDMA MTK_M4U_ID(SMI_L19_ID, 1) +#define M4U_L19_P2_DVP_RDMA MTK_M4U_ID(SMI_L19_ID, 2) +#define M4U_L19_P3_DVP_WDMA MTK_M4U_ID(SMI_L19_ID, 3) + +/* Larb20 -- ipesys */ +#define M4U_L20_P0_FDVT_RDA_0 MTK_M4U_ID(SMI_L20_ID, 0) +#define M4U_L20_P1_FDVT_RDB_0 MTK_M4U_ID(SMI_L20_ID, 1) +#define M4U_L20_P2_FDVT_WRA_0 MTK_M4U_ID(SMI_L20_ID, 2) +#define M4U_L20_P3_FDVT_WRB_0 MTK_M4U_ID(SMI_L20_ID, 3) +#define M4U_L20_P4_RSC_RDMA MTK_M4U_ID(SMI_L20_ID, 4) +#define M4U_L20_P5_RSC_WDMA MTK_M4U_ID(SMI_L20_ID, 5) + +/* fake larb21 for gce */ +#define M4U_L21_GCE_DM MTK_M4U_ID(21, 0) +#define M4U_L21_GCE_MM MTK_M4U_ID(21, 1) + +/* fake larb & port for svp and dual svp and wfd */ +#define M4U_PORT_SVP_HEAP MTK_M4U_ID(22, 0) +#define M4U_PORT_DUAL_SVP_HEAP MTK_M4U_ID(22, 1) +#define M4U_PORT_WFD_HEAP MTK_M4U_ID(22, 2) + +/* fake larb0 for apu */ +#define M4U_L0_APU_DATA MTK_M4U_ID(0, 0) +#define M4U_L0_APU_CODE MTK_M4U_ID(0, 1) +#define M4U_L0_APU_SECURE MTK_M4U_ID(0, 2) +#define M4U_L0_APU_VLM MTK_M4U_ID(0, 3) + +/* infra/peri */ +#define IFR_IOMMU_PORT_PCIE_0 MTK_IFAIOMMU_PERI_ID(0, 26) + +#endif -- 2.46.0 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 1/3] dt-bindings: mediatek: mt8189: Add bindings for MM & APU & INFRA IOMMU 2025-08-07 9:57 ` [PATCH 1/3] dt-bindings: mediatek: mt8189: Add bindings for MM & APU & INFRA IOMMU zhengnan chen @ 2025-08-07 15:23 ` Matthias Brugger 2025-08-07 16:12 ` Conor Dooley 1 sibling, 0 replies; 9+ messages in thread From: Matthias Brugger @ 2025-08-07 15:23 UTC (permalink / raw) To: zhengnan chen, Yong Wu, Joerg Roedel, Will Deacon, Robin Murphy, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno Cc: iommu, linux-mediatek, devicetree, linux-kernel, linux-arm-kernel, Project_Global_Chrome_Upstream_Group On 07/08/2025 11:57, zhengnan chen wrote: > From: "zhengnan chen" <zhengnan.chen@mediatek.com> > > There are three iommu in total, namely MM_IOMMU, APU_IOMMU, INFRA_IOMMU, > Add bindings for them. > > Signed-off-by: zhengnan chen <zhengnan.chen@mediatek.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> > --- > .../bindings/iommu/mediatek,iommu.yaml | 7 + > .../memory/mediatek,mt8189-memory-port.h | 283 ++++++++++++++++++ > 2 files changed, 290 insertions(+) > create mode 100644 include/dt-bindings/memory/mediatek,mt8189-memory-port.h > > diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml > index 75750c64157c..32ca618c08dc 100644 > --- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml > +++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml > @@ -82,6 +82,9 @@ properties: > - mediatek,mt8188-iommu-vdo # generation two > - mediatek,mt8188-iommu-vpp # generation two > - mediatek,mt8188-iommu-infra # generation two > + - mediatek,mt8189-iommu-apu # generation two > + - mediatek,mt8189-iommu-infra # generation two > + - mediatek,mt8189-iommu-mm # generation two > - mediatek,mt8192-m4u # generation two > - mediatek,mt8195-iommu-vdo # generation two > - mediatek,mt8195-iommu-vpp # generation two > @@ -128,6 +131,7 @@ properties: > This is the mtk_m4u_id according to the HW. Specifies the mtk_m4u_id as > defined in > dt-binding/memory/mediatek,mt8188-memory-port.h for mt8188, > + dt-binding/memory/mediatek,mt8189-memory-port.h for mt8189, > dt-binding/memory/mt2701-larb-port.h for mt2701 and mt7623, > dt-binding/memory/mt2712-larb-port.h for mt2712, > dt-binding/memory/mt6779-larb-port.h for mt6779, > @@ -164,6 +168,7 @@ allOf: > - mediatek,mt8186-iommu-mm > - mediatek,mt8188-iommu-vdo > - mediatek,mt8188-iommu-vpp > + - mediatek,mt8189-iommu-mm > - mediatek,mt8192-m4u > - mediatek,mt8195-iommu-vdo > - mediatek,mt8195-iommu-vpp > @@ -180,6 +185,7 @@ allOf: > - mediatek,mt8186-iommu-mm > - mediatek,mt8188-iommu-vdo > - mediatek,mt8188-iommu-vpp > + - mediatek,mt8189-iommu-mm > - mediatek,mt8192-m4u > - mediatek,mt8195-iommu-vdo > - mediatek,mt8195-iommu-vpp > @@ -208,6 +214,7 @@ allOf: > contains: > enum: > - mediatek,mt8188-iommu-infra > + - mediatek,mt8189-iommu-infra > - mediatek,mt8195-iommu-infra > > then: > diff --git a/include/dt-bindings/memory/mediatek,mt8189-memory-port.h b/include/dt-bindings/memory/mediatek,mt8189-memory-port.h > new file mode 100644 > index 000000000000..849fead3d0f7 > --- /dev/null > +++ b/include/dt-bindings/memory/mediatek,mt8189-memory-port.h > @@ -0,0 +1,283 @@ > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ > +/* > + * Copyright (c) 2025 MediaTek Inc. > + * Author: Zhengnan chen <zhengnan.chen@mediatek.com> > + */ > +#ifndef _DT_BINDINGS_MEMORY_MEDIATEK_MT8189_MEMORY_PORT_H_ > +#define _DT_BINDINGS_MEMORY_MEDIATEK_MT8189_MEMORY_PORT_H_ > + > +#include <dt-bindings/memory/mtk-memory-port.h> > + > +#define SMI_L0_ID (0) > +#define SMI_L1_ID (1) > +#define SMI_L2_ID (2) > +#define SMI_L4_ID (3) > +#define SMI_L7_ID (4) > +#define SMI_L9_ID (5) > +#define SMI_L11_ID (6) > +#define SMI_L13_ID (7) > +#define SMI_L14_ID (8) > +#define SMI_L16_ID (9) > +#define SMI_L17_ID (10) > +#define SMI_L19_ID (11) > +#define SMI_L20_ID (12) > + > +/* > + * MM IOMMU supports 16GB dma address. We separate it to four ranges: > + * 0 ~ 4G; 4G ~ 8G; 8G ~ 12G; 12G ~ 16G, we could adjust these masters > + * locate in anyone region. BUT: > + * a) Make sure all the ports inside a larb are in one range. > + * b) The iova of any master can NOT cross the 4G/8G/12G boundary. > + * > + * This is the suggested mapping in this SoC: > + * > + * modules dma-address-region larbs-ports > + * disp/mdp 0 ~ 4G larb0/1/2 > + * vcodec 4G ~ 8G larb4/7 > + * imgsys/cam/ipesys 8G ~ 12G the other larbs. > + * N/A 12G ~ 16G > + */ > + > +/* Larb0 -- disp */ > +#define M4U_L0_P0_DISP_OVL0_4L_HDR MTK_M4U_ID(SMI_L0_ID, 0) > +#define M4U_L0_P1_DISP_OVL0_4L_RDMA0 MTK_M4U_ID(SMI_L0_ID, 1) > +#define M4U_L0_P2_DISP_OVL1_4L_RDMA1 MTK_M4U_ID(SMI_L0_ID, 2) > +#define M4U_L0_P3_DISP_OVL0_4L_RDMA2 MTK_M4U_ID(SMI_L0_ID, 3) > +#define M4U_L0_P4_DISP_OVL1_4L_RDMA3 MTK_M4U_ID(SMI_L0_ID, 4) > +#define M4U_L0_P5_DISP_RDMA0 MTK_M4U_ID(SMI_L0_ID, 5) > +#define M4U_L0_P6_DISP_WDMA0 MTK_M4U_ID(SMI_L0_ID, 6) > +#define M4U_L0_P7_DISP_FAKE_ENG0 MTK_M4U_ID(SMI_L0_ID, 7) > + > +/* Larb1 -- disp */ > +#define M4U_L1_P0_DISP_OVL1_4L_HDR MTK_M4U_ID(SMI_L1_ID, 0) > +#define M4U_L1_P1_DISP_OVL1_4L_RDMA0 MTK_M4U_ID(SMI_L1_ID, 1) > +#define M4U_L1_P2_DISP_OVL0_4L_RDMA1 MTK_M4U_ID(SMI_L1_ID, 2) > +#define M4U_L1_P3_DISP_OVL1_4L_RDMA2 MTK_M4U_ID(SMI_L1_ID, 3) > +#define M4U_L1_P4_DISP_OVL0_4L_RDMA3 MTK_M4U_ID(SMI_L1_ID, 4) > +#define M4U_L1_P5_DISP_RDMA1 MTK_M4U_ID(SMI_L1_ID, 5) > +#define M4U_L1_P6_DISP_WDMA1 MTK_M4U_ID(SMI_L1_ID, 6) > +#define M4U_L1_P7_DISP_FAKE_ENG1 MTK_M4U_ID(SMI_L1_ID, 7) > + > +/* Larb2 -- mmlsys(mdp) */ > +#define M4U_L2_P0_MDP_RDMA0 MTK_M4U_ID(SMI_L2_ID, 0) > +#define M4U_L2_P1_MDP_RDMA1 MTK_M4U_ID(SMI_L2_ID, 1) > +#define M4U_L2_P2_MDP_WROT0 MTK_M4U_ID(SMI_L2_ID, 2) > +#define M4U_L2_P3_MDP_WROT1 MTK_M4U_ID(SMI_L2_ID, 3) > +#define M4U_L2_P4_MDP_DUMMY0 MTK_M4U_ID(SMI_L2_ID, 4) > +#define M4U_L2_P5_MDP_DUMMY1 MTK_M4U_ID(SMI_L2_ID, 5) > +#define M4U_L2_P6_MDP_RDMA2 MTK_M4U_ID(SMI_L2_ID, 6) > +#define M4U_L2_P7_MDP_RDMA3 MTK_M4U_ID(SMI_L2_ID, 7) > +#define M4U_L2_P8_MDP_WROT2 MTK_M4U_ID(SMI_L2_ID, 8) > +#define M4U_L2_P9_MDP_WROT3 MTK_M4U_ID(SMI_L2_ID, 9) > +#define M4U_L2_P10_DISP_FAKE0 MTK_M4U_ID(SMI_L2_ID, 10) > + > +/* Larb3: null */ > + > +/* Larb4 -- vdec */ > +#define M4U_L4_P0_HW_VDEC_MC_EXT MTK_M4U_ID(SMI_L4_ID, 0) > +#define M4U_L4_P1_HW_VDEC_UFO_EXT MTK_M4U_ID(SMI_L4_ID, 1) > +#define M4U_L4_P2_HW_VDEC_PP_EXT MTK_M4U_ID(SMI_L4_ID, 2) > +#define M4U_L4_P3_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(SMI_L4_ID, 3) > +#define M4U_L4_P4_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(SMI_L4_ID, 4) > +#define M4U_L4_P5_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(SMI_L4_ID, 5) > +#define M4U_L4_P6_HW_VDEC_TILE_EXT MTK_M4U_ID(SMI_L4_ID, 6) > +#define M4U_L4_P7_HW_VDEC_VLD_EXT MTK_M4U_ID(SMI_L4_ID, 7) > +#define M4U_L4_P8_HW_VDEC_VLD2_EXT MTK_M4U_ID(SMI_L4_ID, 8) > +#define M4U_L4_P9_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(SMI_L4_ID, 9) > +#define M4U_L4_P10_HW_VDEC_RG_CTRL_DMA_EXT MTK_M4U_ID(SMI_L4_ID, 10) > +#define M4U_L4_P11_HW_VDEC_UFO_ENC_EXT MTK_M4U_ID(SMI_L4_ID, 11) > + > +/* Larb5: null */ > + > +/* Larb6: null */ > + > +/* Larb7 -- venc */ > +#define M4U_L7_P0_VENC_RCPU MTK_M4U_ID(SMI_L7_ID, 0) > +#define M4U_L7_P1_VENC_REC MTK_M4U_ID(SMI_L7_ID, 1) > +#define M4U_L7_P2_VENC_BSDMA MTK_M4U_ID(SMI_L7_ID, 2) > +#define M4U_L7_P3_VENC_SV_COMV MTK_M4U_ID(SMI_L7_ID, 3) > +#define M4U_L7_P4_VENC_RD_COMV MTK_M4U_ID(SMI_L7_ID, 4) > +#define M4U_L7_P5_JPGENC_Y_RDMA MTK_M4U_ID(SMI_L7_ID, 5) > +#define M4U_L7_P6_JPGENC_C_RDMA MTK_M4U_ID(SMI_L7_ID, 6) > +#define M4U_L7_P7_JPGENC_Q_RDMA MTK_M4U_ID(SMI_L7_ID, 7) > +#define M4U_L7_P8_VENC_SUB_W_LUMA MTK_M4U_ID(SMI_L7_ID, 8) > +#define M4U_L7_P9_JPGENC_BSDMA MTK_M4U_ID(SMI_L7_ID, 9) > +#define M4U_L7_P10_VENC_CUR_LUMA MTK_M4U_ID(SMI_L7_ID, 10) > +#define M4U_L7_P11_VENC_CUR_CHROMA MTK_M4U_ID(SMI_L7_ID, 11) > +#define M4U_L7_P12_VENC_REF_LUMA MTK_M4U_ID(SMI_L7_ID, 12) > +#define M4U_L7_P13_VENC_REF_CHROMA MTK_M4U_ID(SMI_L7_ID, 13) > +#define M4U_L7_P14_VENC_SUB_R_LUMA MTK_M4U_ID(SMI_L7_ID, 14) > +#define M4U_L7_P15_JPGDEC_WDMA MTK_M4U_ID(SMI_L7_ID, 15) > +#define M4U_L7_P16_JPGDEC_BSDMA MTK_M4U_ID(SMI_L7_ID, 16) > +#define M4U_L7_P17_JPGDEC_HUFF_OFFSET MTK_M4U_ID(SMI_L7_ID, 17) > + > +/* Larb8: null */ > + > +/* Larb9 --imgsys */ > +#define M4U_L9_P0_IMGI_D1 MTK_M4U_ID(SMI_L9_ID, 0) > +#define M4U_L9_P1_IMGBI_D1 MTK_M4U_ID(SMI_L9_ID, 1) > +#define M4U_L9_P2_DMGI_D1 MTK_M4U_ID(SMI_L9_ID, 2) > +#define M4U_L9_P3_DEPI_D1 MTK_M4U_ID(SMI_L9_ID, 3) > +#define M4U_L9_P4_LCE_D1 MTK_M4U_ID(SMI_L9_ID, 4) > +#define M4U_L9_P5_SMTI_D1 MTK_M4U_ID(SMI_L9_ID, 5) > +#define M4U_L9_P6_SMTO_D2 MTK_M4U_ID(SMI_L9_ID, 6) > +#define M4U_L9_P7_SMTO_D1 MTK_M4U_ID(SMI_L9_ID, 7) > +#define M4U_L9_P8_CRZO_D1 MTK_M4U_ID(SMI_L9_ID, 8) > +#define M4U_L9_P9_IMG3O_D1 MTK_M4U_ID(SMI_L9_ID, 9) > +#define M4U_L9_P10_VIPI_D1 MTK_M4U_ID(SMI_L9_ID, 10) > +#define M4U_L9_P11_SMTI_D5 MTK_M4U_ID(SMI_L9_ID, 11) > +#define M4U_L9_P12_TIMGO_D1 MTK_M4U_ID(SMI_L9_ID, 12) > +#define M4U_L9_P13_UFBC_W0 MTK_M4U_ID(SMI_L9_ID, 13) > +#define M4U_L9_P14_UFBC_R0 MTK_M4U_ID(SMI_L9_ID, 14) > +#define M4U_L9_P15_WPE_RDMA1 MTK_M4U_ID(SMI_L9_ID, 15) > +#define M4U_L9_P16_WPE_RDMA0 MTK_M4U_ID(SMI_L9_ID, 16) > +#define M4U_L9_P17_WPE_WDMA MTK_M4U_ID(SMI_L9_ID, 17) > +#define M4U_L9_P18_MFB_RDMA0 MTK_M4U_ID(SMI_L9_ID, 18) > +#define M4U_L9_P19_MFB_RDMA1 MTK_M4U_ID(SMI_L9_ID, 19) > +#define M4U_L9_P20_MFB_RDMA2 MTK_M4U_ID(SMI_L9_ID, 20) > +#define M4U_L9_P21_MFB_RDMA3 MTK_M4U_ID(SMI_L9_ID, 21) > +#define M4U_L9_P22_MFB_RDMA4 MTK_M4U_ID(SMI_L9_ID, 22) > +#define M4U_L9_P23_MFB_RDMA5 MTK_M4U_ID(SMI_L9_ID, 23) > +#define M4U_L9_P24_MFB_WDMA0 MTK_M4U_ID(SMI_L9_ID, 24) > +#define M4U_L9_P25_MFB_WDMA1 MTK_M4U_ID(SMI_L9_ID, 25) > +#define M4U_L9_P26_RESERVE6 MTK_M4U_ID(SMI_L9_ID, 26) > +#define M4U_L9_P27_RESERVE7 MTK_M4U_ID(SMI_L9_ID, 27) > +#define M4U_L9_P28_RESERVE8 MTK_M4U_ID(SMI_L9_ID, 28) > + > +/* Larb10: null */ > + > +/* Larb11 -- imgsys */ > +#define M4U_L11_P0_IMGI_D1 MTK_M4U_ID(SMI_L11_ID, 0) > +#define M4U_L11_P1_IMGBI_D1 MTK_M4U_ID(SMI_L11_ID, 1) > +#define M4U_L11_P2_DMGI_D1 MTK_M4U_ID(SMI_L11_ID, 2) > +#define M4U_L11_P3_DEPI_D1 MTK_M4U_ID(SMI_L11_ID, 3) > +#define M4U_L11_P4_LCE_D1 MTK_M4U_ID(SMI_L11_ID, 4) > +#define M4U_L11_P5_SMTI_D1 MTK_M4U_ID(SMI_L11_ID, 5) > +#define M4U_L11_P6_SMTO_D2 MTK_M4U_ID(SMI_L11_ID, 6) > +#define M4U_L11_P7_SMTO_D1 MTK_M4U_ID(SMI_L11_ID, 7) > +#define M4U_L11_P8_CRZO_D1 MTK_M4U_ID(SMI_L11_ID, 8) > +#define M4U_L11_P9_IMG3O_D1 MTK_M4U_ID(SMI_L11_ID, 9) > +#define M4U_L11_P10_VIPI_D1 MTK_M4U_ID(SMI_L11_ID, 10) > +#define M4U_L11_P11_SMTI_D5 MTK_M4U_ID(SMI_L11_ID, 11) > +#define M4U_L11_P12_TIMGO_D1 MTK_M4U_ID(SMI_L11_ID, 12) > +#define M4U_L11_P13_UFBC_W0 MTK_M4U_ID(SMI_L11_ID, 13) > +#define M4U_L11_P14_UFBC_R0 MTK_M4U_ID(SMI_L11_ID, 14) > +#define M4U_L11_P15_WPE_RDMA1 MTK_M4U_ID(SMI_L11_ID, 15) > +#define M4U_L11_P16_WPE_RDMA0 MTK_M4U_ID(SMI_L11_ID, 16) > +#define M4U_L11_P17_WPE_WDMA MTK_M4U_ID(SMI_L11_ID, 17) > +#define M4U_L11_P18_MFB_RDMA0 MTK_M4U_ID(SMI_L11_ID, 18) > +#define M4U_L11_P19_MFB_RDMA1 MTK_M4U_ID(SMI_L11_ID, 19) > +#define M4U_L11_P20_MFB_RDMA2 MTK_M4U_ID(SMI_L11_ID, 20) > +#define M4U_L11_P21_MFB_RDMA3 MTK_M4U_ID(SMI_L11_ID, 21) > +#define M4U_L11_P22_MFB_RDMA4 MTK_M4U_ID(SMI_L11_ID, 22) > +#define M4U_L11_P23_MFB_RDMA5 MTK_M4U_ID(SMI_L11_ID, 23) > +#define M4U_L11_P24_MFB_WDMA0 MTK_M4U_ID(SMI_L11_ID, 24) > +#define M4U_L11_P25_MFB_WDMA1 MTK_M4U_ID(SMI_L11_ID, 25) > +#define M4U_L11_P26_RESERVE6 MTK_M4U_ID(SMI_L11_ID, 26) > +#define M4U_L11_P27_RESERVE7 MTK_M4U_ID(SMI_L11_ID, 27) > +#define M4U_L11_P28_RESERVE8 MTK_M4U_ID(SMI_L11_ID, 28) > + > +/* Larb12: null */ > + > +/* Larb13 -- cam */ > +#define M4U_L13_P0_MRAWI MTK_M4U_ID(SMI_L13_ID, 0) > +#define M4U_L13_P1_MRAWO_0 MTK_M4U_ID(SMI_L13_ID, 1) > +#define M4U_L13_P2_MRAWO_1 MTK_M4U_ID(SMI_L13_ID, 2) > +#define M4U_L13_P3_CAMSV_1 MTK_M4U_ID(SMI_L13_ID, 3) > +#define M4U_L13_P4_CAMSV_2 MTK_M4U_ID(SMI_L13_ID, 4) > +#define M4U_L13_P5_CAMSV_3 MTK_M4U_ID(SMI_L13_ID, 5) > +#define M4U_L13_P6_CAMSV_4 MTK_M4U_ID(SMI_L13_ID, 6) > +#define M4U_L13_P7_CAMSV_5 MTK_M4U_ID(SMI_L13_ID, 7) > +#define M4U_L13_P8_CAMSV_6 MTK_M4U_ID(SMI_L13_ID, 8) > +#define M4U_L13_P9_CCUI MTK_M4U_ID(SMI_L13_ID, 9) > +#define M4U_L13_P10_CCUO MTK_M4U_ID(SMI_L13_ID, 10) > +#define M4U_L13_P11_FAKE MTK_M4U_ID(SMI_L13_ID, 11) > +#define M4U_L13_P12_PDAI_0 MTK_M4U_ID(SMI_L13_ID, 12) > +#define M4U_L13_P13_PDAI_1 MTK_M4U_ID(SMI_L13_ID, 13) > +#define M4U_L13_P14_PDAO MTK_M4U_ID(SMI_L13_ID, 14) > + > +/* Larb14 -- cam */ > +#define M4U_L14_P0_RESERVE MTK_M4U_ID(SMI_L14_ID, 0) > +#define M4U_L14_P1_RESERVE MTK_M4U_ID(SMI_L14_ID, 1) > +#define M4U_L14_P2_RESERVE MTK_M4U_ID(SMI_L14_ID, 2) > +#define M4U_L14_P3_CAMSV_0 MTK_M4U_ID(SMI_L14_ID, 3) > +#define M4U_L14_P4_CCUI MTK_M4U_ID(SMI_L14_ID, 4) > +#define M4U_L14_P5_CCUO MTK_M4U_ID(SMI_L14_ID, 5) > +#define M4U_L14_P6_CAMSV_7 MTK_M4U_ID(SMI_L14_ID, 6) > +#define M4U_L14_P7_CAMSV_8 MTK_M4U_ID(SMI_L14_ID, 7) > +#define M4U_L14_P8_CAMSV_9 MTK_M4U_ID(SMI_L14_ID, 8) > +#define M4U_L14_P9_CAMSV_10 MTK_M4U_ID(SMI_L14_ID, 9) > + > +/* Larb15: null */ > + > +/* Larb16 -- cam */ > +#define M4U_L16_P0_IMGO_R1_A MTK_M4U_ID(SMI_L16_ID, 0) > +#define M4U_L16_P1_RRZO_R1_A MTK_M4U_ID(SMI_L16_ID, 1) > +#define M4U_L16_P2_CQI_R1_A MTK_M4U_ID(SMI_L16_ID, 2) > +#define M4U_L16_P3_BPCI_R1_A MTK_M4U_ID(SMI_L16_ID, 3) > +#define M4U_L16_P4_YUVO_R1_A MTK_M4U_ID(SMI_L16_ID, 4) > +#define M4U_L16_P5_UFDI_R2_A MTK_M4U_ID(SMI_L16_ID, 5) > +#define M4U_L16_P6_RAWI_R2_A MTK_M4U_ID(SMI_L16_ID, 6) > +#define M4U_L16_P7_RAWI_R3_A MTK_M4U_ID(SMI_L16_ID, 7) > +#define M4U_L16_P8_AAO_R1_A MTK_M4U_ID(SMI_L16_ID, 8) > +#define M4U_L16_P9_AFO_R1_A MTK_M4U_ID(SMI_L16_ID, 9) > +#define M4U_L16_P10_FLKO_R1_A MTK_M4U_ID(SMI_L16_ID, 10) > +#define M4U_L16_P11_LCESO_R1_A MTK_M4U_ID(SMI_L16_ID, 11) > +#define M4U_L16_P12_CRZO_R1_A MTK_M4U_ID(SMI_L16_ID, 12) > +#define M4U_L16_P13_LTMSO_R1_A MTK_M4U_ID(SMI_L16_ID, 13) > +#define M4U_L16_P14_RSSO_R1_A MTK_M4U_ID(SMI_L16_ID, 14) > +#define M4U_L16_P15_AAHO_R1_A MTK_M4U_ID(SMI_L16_ID, 15) > +#define M4U_L16_P16_LSCI_R1_A MTK_M4U_ID(SMI_L16_ID, 16) > + > +/* Larb17 -- cam */ > +#define M4U_L17_P0_IMGO_R1_B MTK_M4U_ID(SMI_L17_ID, 0) > +#define M4U_L17_P1_RRZO_R1_B MTK_M4U_ID(SMI_L17_ID, 1) > +#define M4U_L17_P2_CQI_R1_B MTK_M4U_ID(SMI_L17_ID, 2) > +#define M4U_L17_P3_BPCI_R1_B MTK_M4U_ID(SMI_L17_ID, 3) > +#define M4U_L17_P4_YUVO_R1_B MTK_M4U_ID(SMI_L17_ID, 4) > +#define M4U_L17_P5_UFDI_R2_B MTK_M4U_ID(SMI_L17_ID, 5) > +#define M4U_L17_P6_RAWI_R2_B MTK_M4U_ID(SMI_L17_ID, 6) > +#define M4U_L17_P7_RAWI_R3_B MTK_M4U_ID(SMI_L17_ID, 7) > +#define M4U_L17_P8_AAO_R1_B MTK_M4U_ID(SMI_L17_ID, 8) > +#define M4U_L17_P9_AFO_R1_B MTK_M4U_ID(SMI_L17_ID, 9) > +#define M4U_L17_P10_FLKO_R1_B MTK_M4U_ID(SMI_L17_ID, 10) > +#define M4U_L17_P11_LCESO_R1_B MTK_M4U_ID(SMI_L17_ID, 11) > +#define M4U_L17_P12_CRZO_R1_B MTK_M4U_ID(SMI_L17_ID, 12) > +#define M4U_L17_P13_LTMSO_R1_B MTK_M4U_ID(SMI_L17_ID, 13) > +#define M4U_L17_P14_RSSO_R1_B MTK_M4U_ID(SMI_L17_ID, 14) > +#define M4U_L17_P15_AAHO_R1_B MTK_M4U_ID(SMI_L17_ID, 15) > +#define M4U_L17_P16_LSCI_R1_B MTK_M4U_ID(SMI_L17_ID, 16) > + > +/* Larb19 -- ipesys */ > +#define M4U_L19_P0_DVS_RDMA MTK_M4U_ID(SMI_L19_ID, 0) > +#define M4U_L19_P1_DVS_WDMA MTK_M4U_ID(SMI_L19_ID, 1) > +#define M4U_L19_P2_DVP_RDMA MTK_M4U_ID(SMI_L19_ID, 2) > +#define M4U_L19_P3_DVP_WDMA MTK_M4U_ID(SMI_L19_ID, 3) > + > +/* Larb20 -- ipesys */ > +#define M4U_L20_P0_FDVT_RDA_0 MTK_M4U_ID(SMI_L20_ID, 0) > +#define M4U_L20_P1_FDVT_RDB_0 MTK_M4U_ID(SMI_L20_ID, 1) > +#define M4U_L20_P2_FDVT_WRA_0 MTK_M4U_ID(SMI_L20_ID, 2) > +#define M4U_L20_P3_FDVT_WRB_0 MTK_M4U_ID(SMI_L20_ID, 3) > +#define M4U_L20_P4_RSC_RDMA MTK_M4U_ID(SMI_L20_ID, 4) > +#define M4U_L20_P5_RSC_WDMA MTK_M4U_ID(SMI_L20_ID, 5) > + > +/* fake larb21 for gce */ > +#define M4U_L21_GCE_DM MTK_M4U_ID(21, 0) > +#define M4U_L21_GCE_MM MTK_M4U_ID(21, 1) > + > +/* fake larb & port for svp and dual svp and wfd */ > +#define M4U_PORT_SVP_HEAP MTK_M4U_ID(22, 0) > +#define M4U_PORT_DUAL_SVP_HEAP MTK_M4U_ID(22, 1) > +#define M4U_PORT_WFD_HEAP MTK_M4U_ID(22, 2) > + > +/* fake larb0 for apu */ > +#define M4U_L0_APU_DATA MTK_M4U_ID(0, 0) > +#define M4U_L0_APU_CODE MTK_M4U_ID(0, 1) > +#define M4U_L0_APU_SECURE MTK_M4U_ID(0, 2) > +#define M4U_L0_APU_VLM MTK_M4U_ID(0, 3) > + > +/* infra/peri */ > +#define IFR_IOMMU_PORT_PCIE_0 MTK_IFAIOMMU_PERI_ID(0, 26) > + > +#endif ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 1/3] dt-bindings: mediatek: mt8189: Add bindings for MM & APU & INFRA IOMMU 2025-08-07 9:57 ` [PATCH 1/3] dt-bindings: mediatek: mt8189: Add bindings for MM & APU & INFRA IOMMU zhengnan chen 2025-08-07 15:23 ` Matthias Brugger @ 2025-08-07 16:12 ` Conor Dooley 1 sibling, 0 replies; 9+ messages in thread From: Conor Dooley @ 2025-08-07 16:12 UTC (permalink / raw) To: zhengnan chen Cc: Yong Wu, Joerg Roedel, Will Deacon, Robin Murphy, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno, iommu, linux-mediatek, devicetree, linux-kernel, linux-arm-kernel, Project_Global_Chrome_Upstream_Group [-- Attachment #1: Type: text/plain, Size: 344 bytes --] On Thu, Aug 07, 2025 at 05:57:46PM +0800, zhengnan chen wrote: > From: "zhengnan chen" <zhengnan.chen@mediatek.com> > > There are three iommu in total, namely MM_IOMMU, APU_IOMMU, INFRA_IOMMU, > Add bindings for them. > > Signed-off-by: zhengnan chen <zhengnan.chen@mediatek.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 2/3] iommu/mediatek: Add a flag DL_WITH_MULTI_LARB 2025-08-07 9:57 [PATCH 0/3] MT8189 IOMMU SUPPORT zhengnan chen 2025-08-07 9:57 ` [PATCH 1/3] dt-bindings: mediatek: mt8189: Add bindings for MM & APU & INFRA IOMMU zhengnan chen @ 2025-08-07 9:57 ` zhengnan chen 2025-08-07 15:24 ` Matthias Brugger 2025-08-10 7:09 ` Yong Wu (吴勇) 2025-08-07 9:57 ` [PATCH 3/3] iommu/mediatek: Add support for mt8189 zhengnan chen 2 siblings, 2 replies; 9+ messages in thread From: zhengnan chen @ 2025-08-07 9:57 UTC (permalink / raw) To: Yong Wu, Joerg Roedel, Will Deacon, Robin Murphy, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno Cc: iommu, linux-mediatek, devicetree, linux-kernel, linux-arm-kernel, Project_Global_Chrome_Upstream_Group, zhengnan chen From: "zhengnan chen" <zhengnan.chen@mediatek.com> Add DL_WITH_MULTI_LARB flag to support the HW which connect with multiple larbs. Prepare for mt8189. In mt8189, the display connect with larb1 and larb2 at the same time. Thus, we should add link between disp-dev with these two larbs. Signed-off-by: zhengnan chen <zhengnan.chen@mediatek.com> --- drivers/iommu/mtk_iommu.c | 56 ++++++++++++++++++++++++++++++--------- 1 file changed, 43 insertions(+), 13 deletions(-) diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index 0e0285348d2b..7af47c59b10b 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -147,6 +147,7 @@ #define TF_PORT_TO_ADDR_MT8173 BIT(18) #define INT_ID_PORT_WIDTH_6 BIT(19) #define CFG_IFA_MASTER_IN_ATF BIT(20) +#define DL_WITH_MULTI_LARB BIT(21) #define MTK_IOMMU_HAS_FLAG_MASK(pdata, _x, mask) \ ((((pdata)->flags) & (mask)) == (_x)) @@ -865,6 +866,7 @@ static struct iommu_device *mtk_iommu_probe_device(struct device *dev) struct mtk_iommu_data *data = dev_iommu_priv_get(dev); struct device_link *link; struct device *larbdev; + unsigned long larbid_msk = 0; unsigned int larbid, larbidx, i; if (!MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) @@ -872,30 +874,50 @@ static struct iommu_device *mtk_iommu_probe_device(struct device *dev) /* * Link the consumer device with the smi-larb device(supplier). - * The device that connects with each a larb is a independent HW. - * All the ports in each a device should be in the same larbs. + * w/DL_WITH_MULTI_LARB: the master may connect with multi larbs, + * we should create device link with each larb. + * w/o DL_WITH_MULTI_LARB: the master must connect with one larb, + * otherwise fail. */ larbid = MTK_M4U_TO_LARB(fwspec->ids[0]); if (larbid >= MTK_LARB_NR_MAX) return ERR_PTR(-EINVAL); + larbid_msk |= BIT(larbid); + for (i = 1; i < fwspec->num_ids; i++) { larbidx = MTK_M4U_TO_LARB(fwspec->ids[i]); - if (larbid != larbidx) { + if (MTK_IOMMU_HAS_FLAG(data->plat_data, DL_WITH_MULTI_LARB)) { + larbid_msk |= BIT(larbidx); + } else if (larbid != larbidx) { dev_err(dev, "Can only use one larb. Fail@larb%d-%d.\n", larbid, larbidx); return ERR_PTR(-EINVAL); } } - larbdev = data->larb_imu[larbid].dev; - if (!larbdev) - return ERR_PTR(-EINVAL); - link = device_link_add(dev, larbdev, - DL_FLAG_PM_RUNTIME | DL_FLAG_STATELESS); - if (!link) - dev_err(dev, "Unable to link %s\n", dev_name(larbdev)); + for_each_set_bit(larbid, &larbid_msk, 32) { + larbdev = data->larb_imu[larbid].dev; + if (!larbdev) + return ERR_PTR(-EINVAL); + + link = device_link_add(dev, larbdev, + DL_FLAG_PM_RUNTIME | DL_FLAG_STATELESS); + if (!link) { + dev_err(dev, "Unable to link %s\n", dev_name(larbdev)); + goto link_remove; + } + } + return &data->iommu; + +link_remove: + for_each_set_bit(i, &larbid_msk, larbid) { + larbdev = data->larb_imu[i].dev; + device_link_remove(dev, larbdev); + } + + return ERR_PTR(-ENODEV); } static void mtk_iommu_release_device(struct device *dev) @@ -903,11 +925,19 @@ static void mtk_iommu_release_device(struct device *dev) struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); struct mtk_iommu_data *data; struct device *larbdev; - unsigned int larbid; + unsigned int larbid, i; + unsigned long larbid_msk = 0; data = dev_iommu_priv_get(dev); - if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) { - larbid = MTK_M4U_TO_LARB(fwspec->ids[0]); + if (!MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) + return; + + for (i = 0; i < fwspec->num_ids; i++) { + larbid = MTK_M4U_TO_LARB(fwspec->ids[i]); + larbid_msk |= BIT(larbid); + } + + for_each_set_bit(larbid, &larbid_msk, 32) { larbdev = data->larb_imu[larbid].dev; device_link_remove(dev, larbdev); } -- 2.46.0 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 2/3] iommu/mediatek: Add a flag DL_WITH_MULTI_LARB 2025-08-07 9:57 ` [PATCH 2/3] iommu/mediatek: Add a flag DL_WITH_MULTI_LARB zhengnan chen @ 2025-08-07 15:24 ` Matthias Brugger 2025-08-10 7:09 ` Yong Wu (吴勇) 1 sibling, 0 replies; 9+ messages in thread From: Matthias Brugger @ 2025-08-07 15:24 UTC (permalink / raw) To: zhengnan chen, Yong Wu, Joerg Roedel, Will Deacon, Robin Murphy, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno Cc: iommu, linux-mediatek, devicetree, linux-kernel, linux-arm-kernel, Project_Global_Chrome_Upstream_Group On 07/08/2025 11:57, zhengnan chen wrote: > From: "zhengnan chen" <zhengnan.chen@mediatek.com> > > Add DL_WITH_MULTI_LARB flag to support the HW which connect with > multiple larbs. Prepare for mt8189. In mt8189, the display connect > with larb1 and larb2 at the same time. Thus, we should add link > between disp-dev with these two larbs. > > Signed-off-by: zhengnan chen <zhengnan.chen@mediatek.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> > --- > drivers/iommu/mtk_iommu.c | 56 ++++++++++++++++++++++++++++++--------- > 1 file changed, 43 insertions(+), 13 deletions(-) > > diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c > index 0e0285348d2b..7af47c59b10b 100644 > --- a/drivers/iommu/mtk_iommu.c > +++ b/drivers/iommu/mtk_iommu.c > @@ -147,6 +147,7 @@ > #define TF_PORT_TO_ADDR_MT8173 BIT(18) > #define INT_ID_PORT_WIDTH_6 BIT(19) > #define CFG_IFA_MASTER_IN_ATF BIT(20) > +#define DL_WITH_MULTI_LARB BIT(21) > > #define MTK_IOMMU_HAS_FLAG_MASK(pdata, _x, mask) \ > ((((pdata)->flags) & (mask)) == (_x)) > @@ -865,6 +866,7 @@ static struct iommu_device *mtk_iommu_probe_device(struct device *dev) > struct mtk_iommu_data *data = dev_iommu_priv_get(dev); > struct device_link *link; > struct device *larbdev; > + unsigned long larbid_msk = 0; > unsigned int larbid, larbidx, i; > > if (!MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) > @@ -872,30 +874,50 @@ static struct iommu_device *mtk_iommu_probe_device(struct device *dev) > > /* > * Link the consumer device with the smi-larb device(supplier). > - * The device that connects with each a larb is a independent HW. > - * All the ports in each a device should be in the same larbs. > + * w/DL_WITH_MULTI_LARB: the master may connect with multi larbs, > + * we should create device link with each larb. > + * w/o DL_WITH_MULTI_LARB: the master must connect with one larb, > + * otherwise fail. > */ > larbid = MTK_M4U_TO_LARB(fwspec->ids[0]); > if (larbid >= MTK_LARB_NR_MAX) > return ERR_PTR(-EINVAL); > > + larbid_msk |= BIT(larbid); > + > for (i = 1; i < fwspec->num_ids; i++) { > larbidx = MTK_M4U_TO_LARB(fwspec->ids[i]); > - if (larbid != larbidx) { > + if (MTK_IOMMU_HAS_FLAG(data->plat_data, DL_WITH_MULTI_LARB)) { > + larbid_msk |= BIT(larbidx); > + } else if (larbid != larbidx) { > dev_err(dev, "Can only use one larb. Fail@larb%d-%d.\n", > larbid, larbidx); > return ERR_PTR(-EINVAL); > } > } > - larbdev = data->larb_imu[larbid].dev; > - if (!larbdev) > - return ERR_PTR(-EINVAL); > > - link = device_link_add(dev, larbdev, > - DL_FLAG_PM_RUNTIME | DL_FLAG_STATELESS); > - if (!link) > - dev_err(dev, "Unable to link %s\n", dev_name(larbdev)); > + for_each_set_bit(larbid, &larbid_msk, 32) { > + larbdev = data->larb_imu[larbid].dev; > + if (!larbdev) > + return ERR_PTR(-EINVAL); > + > + link = device_link_add(dev, larbdev, > + DL_FLAG_PM_RUNTIME | DL_FLAG_STATELESS); > + if (!link) { > + dev_err(dev, "Unable to link %s\n", dev_name(larbdev)); > + goto link_remove; > + } > + } > + > return &data->iommu; > + > +link_remove: > + for_each_set_bit(i, &larbid_msk, larbid) { > + larbdev = data->larb_imu[i].dev; > + device_link_remove(dev, larbdev); > + } > + > + return ERR_PTR(-ENODEV); > } > > static void mtk_iommu_release_device(struct device *dev) > @@ -903,11 +925,19 @@ static void mtk_iommu_release_device(struct device *dev) > struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); > struct mtk_iommu_data *data; > struct device *larbdev; > - unsigned int larbid; > + unsigned int larbid, i; > + unsigned long larbid_msk = 0; > > data = dev_iommu_priv_get(dev); > - if (MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) { > - larbid = MTK_M4U_TO_LARB(fwspec->ids[0]); > + if (!MTK_IOMMU_IS_TYPE(data->plat_data, MTK_IOMMU_TYPE_MM)) > + return; > + > + for (i = 0; i < fwspec->num_ids; i++) { > + larbid = MTK_M4U_TO_LARB(fwspec->ids[i]); > + larbid_msk |= BIT(larbid); > + } > + > + for_each_set_bit(larbid, &larbid_msk, 32) { > larbdev = data->larb_imu[larbid].dev; > device_link_remove(dev, larbdev); > } ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 2/3] iommu/mediatek: Add a flag DL_WITH_MULTI_LARB 2025-08-07 9:57 ` [PATCH 2/3] iommu/mediatek: Add a flag DL_WITH_MULTI_LARB zhengnan chen 2025-08-07 15:24 ` Matthias Brugger @ 2025-08-10 7:09 ` Yong Wu (吴勇) 1 sibling, 0 replies; 9+ messages in thread From: Yong Wu (吴勇) @ 2025-08-10 7:09 UTC (permalink / raw) To: Zhengnan Chen (陈征南), robin.murphy@arm.com, joro@8bytes.org, conor+dt@kernel.org, robh@kernel.org, matthias.bgg@gmail.com, krzk+dt@kernel.org, AngeloGioacchino Del Regno, will@kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, Project_Global_Chrome_Upstream_Group, iommu@lists.linux.dev, devicetree@vger.kernel.org On Thu, 2025-08-07 at 17:57 +0800, zhengnan chen wrote: > From: "zhengnan chen" <zhengnan.chen@mediatek.com> > > Add DL_WITH_MULTI_LARB flag to support the HW which connect with > multiple larbs. Prepare for mt8189. In mt8189, the display connect > with larb1 and larb2 at the same time. Thus, we should add link > between disp-dev with these two larbs. > > Signed-off-by: zhengnan chen <zhengnan.chen@mediatek.com> > --- Reviewed-by: Yong Wu <yong.wu@mediatek.com> ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 3/3] iommu/mediatek: Add support for mt8189 2025-08-07 9:57 [PATCH 0/3] MT8189 IOMMU SUPPORT zhengnan chen 2025-08-07 9:57 ` [PATCH 1/3] dt-bindings: mediatek: mt8189: Add bindings for MM & APU & INFRA IOMMU zhengnan chen 2025-08-07 9:57 ` [PATCH 2/3] iommu/mediatek: Add a flag DL_WITH_MULTI_LARB zhengnan chen @ 2025-08-07 9:57 ` zhengnan chen 2025-08-10 7:09 ` Yong Wu (吴勇) 2 siblings, 1 reply; 9+ messages in thread From: zhengnan chen @ 2025-08-07 9:57 UTC (permalink / raw) To: Yong Wu, Joerg Roedel, Will Deacon, Robin Murphy, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno Cc: iommu, linux-mediatek, devicetree, linux-kernel, linux-arm-kernel, Project_Global_Chrome_Upstream_Group, zhengnan chen From: "zhengnan chen" <zhengnan.chen@mediatek.com> Add support for mt8189 INFRA & APU & MM IOMMUs. Signed-off-by: zhengnan chen <zhengnan.chen@mediatek.com> --- drivers/iommu/mtk_iommu.c | 76 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 76 insertions(+) diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index 7af47c59b10b..8ee1208735bf 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -139,6 +139,7 @@ /* 2 bits: iommu type */ #define MTK_IOMMU_TYPE_MM (0x0 << 13) #define MTK_IOMMU_TYPE_INFRA (0x1 << 13) +#define MTK_IOMMU_TYPE_APU (0x2 << 13) #define MTK_IOMMU_TYPE_MASK (0x3 << 13) /* PM and clock always on. e.g. infra iommu */ #define PM_CLK_AO BIT(15) @@ -173,6 +174,7 @@ enum mtk_iommu_plat { M4U_MT8183, M4U_MT8186, M4U_MT8188, + M4U_MT8189, M4U_MT8192, M4U_MT8195, M4U_MT8365, @@ -337,6 +339,8 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data, unsigned int ban #define MTK_IOMMU_4GB_MODE_REMAP_BASE 0x140000000UL static LIST_HEAD(m4ulist); /* List all the M4U HWs */ +static LIST_HEAD(apulist); /* List the apu iommu HWs */ +static LIST_HEAD(infralist); /* List the iommu_infra HW */ #define for_each_m4u(data, head) list_for_each_entry(data, head, list) @@ -351,6 +355,15 @@ static const struct mtk_iommu_iova_region single_domain[] = { #define MT8192_MULTI_REGION_NR (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) ? \ MT8192_MULTI_REGION_NR_MAX : 1) +static const struct mtk_iommu_iova_region mt8189_multi_dom_apu[] = { + { .iova_base = 0x200000ULL, .size = SZ_512M}, /* APU SECURE */ +#if IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) + { .iova_base = SZ_1G, .size = 0xc0000000}, /* APU CODE */ + { .iova_base = 0x70000000ULL, .size = 0x12600000}, /* APU VLM */ + { .iova_base = SZ_4G, .size = SZ_4G * 3}, /* APU VPU */ +#endif +}; + static const struct mtk_iommu_iova_region mt8192_multi_dom[MT8192_MULTI_REGION_NR] = { { .iova_base = 0x0, .size = MTK_IOMMU_IOVA_SZ_4G}, /* 0 ~ 4G, */ #if IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) @@ -1725,6 +1738,66 @@ static const struct mtk_iommu_plat_data mt8188_data_vpp = { 27, 28 /* ccu0 */, MTK_INVALID_LARBID}, {4, 6}}, }; +static const unsigned int mt8189_apu_region_msk[][MTK_LARB_NR_MAX] = { + [0] = {[0] = BIT(2)}, /* Region0: fake larb 0 APU_SECURE */ + [1] = {[0] = BIT(1)}, /* Region1: fake larb 0 APU_CODE */ + [2] = {[0] = BIT(3)}, /* Region2: fake larb 0 APU_VLM */ + [3] = {[0] = BIT(0)}, /* Region3: fake larb 0 APU_DATA */ +}; + +static const struct mtk_iommu_plat_data mt8189_data_apu = { + .m4u_plat = M4U_MT8189, + .flags = IOVA_34_EN | DCM_DISABLE | + MTK_IOMMU_TYPE_APU | PGTABLE_PA_35_EN, + .hw_list = &apulist, + .inv_sel_reg = REG_MMU_INV_SEL_GEN2, + .banks_num = 1, + .banks_enable = {true}, + .iova_region = mt8189_multi_dom_apu, + .iova_region_nr = ARRAY_SIZE(mt8189_multi_dom_apu), + .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}, {6}, {7}}, + .iova_region_larb_msk = mt8189_apu_region_msk, +}; + +static const struct mtk_iommu_plat_data mt8189_data_infra = { + .m4u_plat = M4U_MT8189, + .flags = WR_THROT_EN | DCM_DISABLE | MTK_IOMMU_TYPE_INFRA | + CFG_IFA_MASTER_IN_ATF | SHARE_PGTABLE | PGTABLE_PA_35_EN, + .hw_list = &infralist, + .banks_num = 1, + .banks_enable = {true}, + .inv_sel_reg = REG_MMU_INV_SEL_GEN2, + .iova_region = single_domain, + .iova_region_nr = ARRAY_SIZE(single_domain), +}; + +static const u32 mt8189_larb_region_msk[MT8192_MULTI_REGION_NR_MAX][MTK_LARB_NR_MAX] = { + [0] = {~0, ~0, ~0, [22] = BIT(0)}, /* Region0: all ports for larb0/1/2 */ + [1] = {[3] = ~0, [4] = ~0}, /* Region1: all ports for larb4(3)/7(4) */ + [2] = {[5] = ~0, [6] = ~0, /* Region2: all ports for larb9(5)/11(6) */ + [7] = ~0, [8] = ~0, /* Region2: all ports for larb13(7)/14(8) */ + [9] = ~0, [10] = ~0, /* Region2: all ports for larb16(9)/17(10) */ + [11] = ~0, [12] = ~0, /* Region2: all ports for larb19(11)/20(12) */ + [21] = ~0}, /* Region2: larb21 fake GCE larb */ +}; + +static const struct mtk_iommu_plat_data mt8189_data_mm = { + .m4u_plat = M4U_MT8189, + .flags = HAS_BCLK | HAS_SUB_COMM_3BITS | OUT_ORDER_WR_EN | + WR_THROT_EN | IOVA_34_EN | MTK_IOMMU_TYPE_MM | + PGTABLE_PA_35_EN | DL_WITH_MULTI_LARB, + .hw_list = &m4ulist, + .inv_sel_reg = REG_MMU_INV_SEL_GEN2, + .banks_num = 5, + .banks_enable = {true, false, false, false, true}, + .iova_region = mt8192_multi_dom, + .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom), + .iova_region_larb_msk = mt8189_larb_region_msk, + .larbid_remap = {{0}, {1}, {21/*GCE_D*/, 21/*GCE_M*/, 2}, + {19, 20, 9, 11}, {7}, {4}, + {13, 17}, {14, 16}}, +}; + static const struct mtk_iommu_plat_data mt8192_data = { .m4u_plat = M4U_MT8192, .flags = HAS_BCLK | HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN | @@ -1826,6 +1899,9 @@ static const struct of_device_id mtk_iommu_of_ids[] = { { .compatible = "mediatek,mt8188-iommu-infra", .data = &mt8188_data_infra}, { .compatible = "mediatek,mt8188-iommu-vdo", .data = &mt8188_data_vdo}, { .compatible = "mediatek,mt8188-iommu-vpp", .data = &mt8188_data_vpp}, + { .compatible = "mediatek,mt8189-iommu-apu", .data = &mt8189_data_apu}, + { .compatible = "mediatek,mt8189-iommu-infra", .data = &mt8189_data_infra}, + { .compatible = "mediatek,mt8189-iommu-mm", .data = &mt8189_data_mm}, { .compatible = "mediatek,mt8192-m4u", .data = &mt8192_data}, { .compatible = "mediatek,mt8195-iommu-infra", .data = &mt8195_data_infra}, { .compatible = "mediatek,mt8195-iommu-vdo", .data = &mt8195_data_vdo}, -- 2.46.0 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 3/3] iommu/mediatek: Add support for mt8189 2025-08-07 9:57 ` [PATCH 3/3] iommu/mediatek: Add support for mt8189 zhengnan chen @ 2025-08-10 7:09 ` Yong Wu (吴勇) 0 siblings, 0 replies; 9+ messages in thread From: Yong Wu (吴勇) @ 2025-08-10 7:09 UTC (permalink / raw) To: Zhengnan Chen (陈征南), robin.murphy@arm.com, joro@8bytes.org, conor+dt@kernel.org, robh@kernel.org, matthias.bgg@gmail.com, krzk+dt@kernel.org, AngeloGioacchino Del Regno, will@kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, Project_Global_Chrome_Upstream_Group, iommu@lists.linux.dev, devicetree@vger.kernel.org On Thu, 2025-08-07 at 17:57 +0800, zhengnan chen wrote: > From: "zhengnan chen" <zhengnan.chen@mediatek.com> > > Add support for mt8189 INFRA & APU & MM IOMMUs. > > Signed-off-by: zhengnan chen <zhengnan.chen@mediatek.com> Splitting this into three patches(apu/mm/infra) may make the patch more readable. > --- > drivers/iommu/mtk_iommu.c | 76 > +++++++++++++++++++++++++++++++++++++++ > 1 file changed, 76 insertions(+) > [snip] > + > +static const struct mtk_iommu_plat_data mt8189_data_mm = { > + .m4u_plat = M4U_MT8189, > + .flags = HAS_BCLK | HAS_SUB_COMM_3BITS | > OUT_ORDER_WR_EN | > + WR_THROT_EN | IOVA_34_EN | MTK_IOMMU_TYPE_MM > | > + PGTABLE_PA_35_EN | DL_WITH_MULTI_LARB, > + .hw_list = &m4ulist, > + .inv_sel_reg = REG_MMU_INV_SEL_GEN2, > + .banks_num = 5, > + .banks_enable = {true, false, false, false, true}, > + .iova_region = mt8192_multi_dom, > + .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom), > + .iova_region_larb_msk = mt8189_larb_region_msk, > + .larbid_remap = {{0}, {1}, {21/*GCE_D*/, 21/*GCE_M*/, 2}, Take care the format, Add space after '/*' > + {19, 20, 9, 11}, {7}, {4}, > + {13, 17}, {14, 16}}, > +}; > + > static const struct mtk_iommu_plat_data mt8192_data = { > .m4u_plat = M4U_MT8192, > .flags = HAS_BCLK | HAS_SUB_COMM_2BITS | > OUT_ORDER_WR_EN | > @@ -1826,6 +1899,9 @@ static const struct of_device_id > mtk_iommu_of_ids[] = { > { .compatible = "mediatek,mt8188-iommu-infra", .data = > &mt8188_data_infra}, > { .compatible = "mediatek,mt8188-iommu-vdo", .data = > &mt8188_data_vdo}, > { .compatible = "mediatek,mt8188-iommu-vpp", .data = > &mt8188_data_vpp}, > + { .compatible = "mediatek,mt8189-iommu-apu", .data = > &mt8189_data_apu}, > + { .compatible = "mediatek,mt8189-iommu-infra", .data = > &mt8189_data_infra}, > + { .compatible = "mediatek,mt8189-iommu-mm", .data = > &mt8189_data_mm}, > { .compatible = "mediatek,mt8192-m4u", .data = &mt8192_data}, > { .compatible = "mediatek,mt8195-iommu-infra", .data = > &mt8195_data_infra}, > { .compatible = "mediatek,mt8195-iommu-vdo", .data = > &mt8195_data_vdo}, ^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2025-08-10 7:10 UTC | newest] Thread overview: 9+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2025-08-07 9:57 [PATCH 0/3] MT8189 IOMMU SUPPORT zhengnan chen 2025-08-07 9:57 ` [PATCH 1/3] dt-bindings: mediatek: mt8189: Add bindings for MM & APU & INFRA IOMMU zhengnan chen 2025-08-07 15:23 ` Matthias Brugger 2025-08-07 16:12 ` Conor Dooley 2025-08-07 9:57 ` [PATCH 2/3] iommu/mediatek: Add a flag DL_WITH_MULTI_LARB zhengnan chen 2025-08-07 15:24 ` Matthias Brugger 2025-08-10 7:09 ` Yong Wu (吴勇) 2025-08-07 9:57 ` [PATCH 3/3] iommu/mediatek: Add support for mt8189 zhengnan chen 2025-08-10 7:09 ` Yong Wu (吴勇)
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