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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-245ed4c7588sm77576235ad.101.2025.08.22.01.43.14 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 22 Aug 2025 01:43:20 -0700 (PDT) Message-ID: <2e3c1559-7da2-4c6e-bcef-eb1e8dfd4c31@oss.qualcomm.com> Date: Fri, 22 Aug 2025 16:43:11 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 08/14] phy: qcom: qmp-usbc: Add DP PHY configuration support for QCS615 To: Dmitry Baryshkov Cc: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kuogee Hsieh , Vinod Koul , Kishon Vijay Abraham I , Philipp Zabel , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, fange.zhang@oss.qualcomm.com, yongxing.mou@oss.qualcomm.com, tingwei.zhang@oss.qualcomm.com, Bjorn Andersson , Konrad Dybcio References: <20250820-add-displayport-support-for-qcs615-platform-v3-0-a43bd25ec39c@oss.qualcomm.com> <20250820-add-displayport-support-for-qcs615-platform-v3-8-a43bd25ec39c@oss.qualcomm.com> From: Xiangxu Yin In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODIwMDAxMyBTYWx0ZWRfX5bJEoU6TDVb3 UgFYixanVDk3woIjiiTb1MlfEGw6AI9254naAWktyfntgAMrZ4xSDGO0M+F5CA/btRrXxqnJTj6 8PWU7hXtqC8Iaa9/3SBr49sbJTx1Z/ykSz4EkzhL8hSMbQTHo2sVsf7uqq2eHbZ1CrxTJBbIC86 LDa2krpQtcYV3HTzXdNXe4X2B6I8J5LjxPOpg3/haDRes3hC6TDmuB/JqY8ISPtCjV4wNrTs2MY GVw3WpWnbBRUWVO8b9LlG8+9p8utEt6c4dogBalsQo6RZLpku4ygOKAdSFzHf71KRhESq0taBDf kiXCe60l/M9JcOjK1gIGGPxokrcl11iaJncqTjSwvNnoruNcl8lmW8Sl9aLuQga9lXfSCV2cLaj YSdHva668UsDden9o0RI4OtZMgJM2w== X-Proofpoint-ORIG-GUID: UhqVwA8__uM_Nc6I9jAq9aRApGCDPZA3 X-Proofpoint-GUID: UhqVwA8__uM_Nc6I9jAq9aRApGCDPZA3 X-Authority-Analysis: v=2.4 cv=SoXJKPO0 c=1 sm=1 tr=0 ts=68a82daa cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=2OwXVqhp2XgA:10 a=EUspDBNiAAAA:8 a=B0UfJI3MrboyiCAuw3UA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-22_03,2025-08-20_03,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 spamscore=0 adultscore=0 lowpriorityscore=0 bulkscore=0 priorityscore=1501 suspectscore=0 malwarescore=0 phishscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2508110000 definitions=main-2508200013 On 8/20/2025 7:16 PM, Dmitry Baryshkov wrote: > On Wed, Aug 20, 2025 at 05:34:50PM +0800, Xiangxu Yin wrote: >> Introduce DisplayPort PHY configuration routines for QCS615, including >> aux channel setup, lane control, voltage swing tuning, clock >> programming and calibration. These callbacks are registered via >> qmp_phy_cfg to enable DP mode on USB/DP switchable Type-C PHYs. >> >> Signed-off-by: Xiangxu Yin >> --- >> drivers/phy/qualcomm/phy-qcom-qmp-dp-phy.h | 1 + >> drivers/phy/qualcomm/phy-qcom-qmp-usbc.c | 251 +++++++++++++++++++++++++++++ >> 2 files changed, 252 insertions(+) >> >> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-dp-phy.h b/drivers/phy/qualcomm/phy-qcom-qmp-dp-phy.h >> index 0ebd405bcaf0cac8215550bfc9b226f30cc43a59..59885616405f878885d0837838a0bac1899fb69f 100644 >> --- a/drivers/phy/qualcomm/phy-qcom-qmp-dp-phy.h >> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-dp-phy.h >> @@ -25,6 +25,7 @@ >> #define QSERDES_DP_PHY_AUX_CFG7 0x03c >> #define QSERDES_DP_PHY_AUX_CFG8 0x040 >> #define QSERDES_DP_PHY_AUX_CFG9 0x044 >> +#define QSERDES_DP_PHY_VCO_DIV 0x068 > This register changes between PHY versions, so you can not declare it here. > > Otherwise LGTM. Ok. This PHY appears to be QMP_DP_PHY_V2, but there's no dedicated header for it yet.  I’ll create |phy-qcom-qmp-dp-phy-v2.h| next patch and define |VCO_DIV| and shared offsets with V3 will be redefined accordingly. > >> >> /* QSERDES COM_BIAS_EN_CLKBUFLR_EN bits */ >> # define QSERDES_V3_COM_BIAS_EN 0x0001