From: David Lechner <dlechner@baylibre.com>
To: Andy Shevchenko <andriy.shevchenko@intel.com>
Cc: "Antoniu Miclaus" <antoniu.miclaus@analog.com>,
"Lars-Peter Clausen" <lars@metafoo.de>,
"Michael Hennerich" <Michael.Hennerich@analog.com>,
"Ramona Gradinariu" <ramona.gradinariu@analog.com>,
"Jonathan Cameron" <jic23@kernel.org>,
"Nuno Sá" <nuno.sa@analog.com>,
"Andy Shevchenko" <andy@kernel.org>,
linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] iio: accel: adxl380: fix FIFO watermark bit 8 always written as 0
Date: Mon, 2 Mar 2026 08:54:52 -0600 [thread overview]
Message-ID: <2e4acc5f-2079-4160-a4d3-6453b48eef03@baylibre.com> (raw)
In-Reply-To: <aaVCuE8rwFikaL5c@ashevche-desk.local>
On 3/2/26 1:56 AM, Andy Shevchenko wrote:
> On Sat, Feb 28, 2026 at 10:50:00AM -0600, David Lechner wrote:
>> On 2/27/26 6:43 AM, Antoniu Miclaus wrote:
>
> ...
>
>>> + !!(fifo_samples & BIT(8))));
>>
>> Technically, this works, but in terms of understanding the code I think
>> fifo_samples >= BIT(8) would make more sense.
>>
>> fifo_samples is a count, not bit flags.
>
> I even would prefer to see in such a case
>
> fifo_samples > (BIT(8) - 1)
>
> that it will define the maximum that fits the HW, or plain number
>
> fifo_samples > 127
>
Now that I looked at the dataheet, I get Jonathan's point.
The reason this is here is that we are filling in a 9-bit value
using 8-bit registers, so the MSB goes in a different register.
So actually, it would probably make the most sense to write
it as `fifo_samples >> 8`.
next prev parent reply other threads:[~2026-03-02 14:54 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-02-27 12:43 [PATCH] iio: accel: adxl380: fix FIFO watermark bit 8 always written as 0 Antoniu Miclaus
2026-02-28 12:03 ` Jonathan Cameron
2026-02-28 16:50 ` David Lechner
2026-03-01 12:02 ` Jonathan Cameron
2026-03-02 7:56 ` Andy Shevchenko
2026-03-02 14:54 ` David Lechner [this message]
2026-03-02 15:03 ` Andy Shevchenko
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