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From: Krzysztof Kozlowski <krzk@kernel.org>
To: E Shattow <e@freeshell.de>,
	linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
	linux-riscv@lists.infradead.org, Rob Herring <robh@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>
Subject: Re: [PATCH v1 1/3] dt-bindings: memory-controllers: add StarFive JH7110 SoC DMC
Date: Mon, 23 Jun 2025 08:44:03 +0200	[thread overview]
Message-ID: <2e53fc11-49eb-420c-ab8e-57e9493c42ba@kernel.org> (raw)
In-Reply-To: <20250606130253.1105273-2-e@freeshell.de>

On 06/06/2025 15:02, E Shattow wrote:
> Document bindings for the JH7110 SoC DMC as implemented in downstream
> U-Boot driver starfive_ddr.c
> 
> Signed-off-by: E Shattow <e@freeshell.de>
> ---
>  .../starfive,jh7110-dmc.yaml                  | 76 +++++++++++++++++++
>  1 file changed, 76 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/memory-controllers/starfive,jh7110-dmc.yaml
> 
> diff --git a/Documentation/devicetree/bindings/memory-controllers/starfive,jh7110-dmc.yaml b/Documentation/devicetree/bindings/memory-controllers/starfive,jh7110-dmc.yaml
> new file mode 100644
> index 000000000000..299c86893db1
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/memory-controllers/starfive,jh7110-dmc.yaml
> @@ -0,0 +1,76 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/memory-controllers/starfive,jh7110-dmc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: StarFive JH7110 DMC
> +
> +maintainers:
> +  - E Shattow <e@freeshell.de>
> +
> +description:
> +  JH7110 DMC as implemented by U-Boot boot loader driver starfive_ddr.c

Bindings are about hardware. Explain the hardware, not drivers.

> +
> +properties:
> +  compatible:
> +    items:
> +      - const: starfive,jh7110-dmc
> +
> +  reg:
> +    minItems: 2

Drop

> +    maxItems: 2

Drop and list items with description instead


> +
> +  clocks:
> +    maxItems: 1
> +
> +  clock-names:
> +    items:
> +      - const: pll1_out
> +
> +  clock-frequency:
> +    enum: [2133, 2800]
> +    default: 2133

Drop clock-frequency. I doubt 2133 Hz is even correct... This is a
legacy property, use common clock framework.

> +
> +  resets:
> +    minItems: 3
> +    maxItems: 3

List the items with description instead

> +
> +  reset-names:
> +    items:
> +      - const: axi
> +      - const: osc
> +      - const: apb
> +
> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +  - clock-names
> +  - clock-frequency
> +  - resets
> +  - reset-names
Best regards,
Krzysztof

  reply	other threads:[~2025-06-23  6:44 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-06-06 13:02 [PATCH v1 0/3] riscv: dts: starfive: jh7110: More U-Boot downstream changes for JH7110 E Shattow
2025-06-06 13:02 ` [PATCH v1 1/3] dt-bindings: memory-controllers: add StarFive JH7110 SoC DMC E Shattow
2025-06-23  6:44   ` Krzysztof Kozlowski [this message]
2025-06-23  6:45   ` Krzysztof Kozlowski
2025-06-23 15:56     ` Conor Dooley
2025-06-23 16:11       ` Krzysztof Kozlowski
2025-06-06 13:02 ` [PATCH v1 2/3] riscv: dts: starfive: jh7110: add memory controller node E Shattow
2025-06-06 13:02 ` [PATCH v1 3/3] riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot loader E Shattow

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