From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EF19032ABC0 for ; Mon, 30 Mar 2026 14:57:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774882639; cv=none; b=B/wj7SeySlxsKED4+YAsrWHTW4qTitk97NXeLiEv5ogiJQw1FARqwvT8hoB61YPCUqksgxGeepC4e03C9w9L4D+n/71z/b46t11Pl2WVs+8NzfsgtIemoLK/bkXnRALUN1ZQ4lzOq5yzJq8dSMLMQZjG0egrwIB+S/WXcE4qvmw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774882639; c=relaxed/simple; bh=1gI6dUoAUj8KI/jS+DQQsDNccGUp1WnD6AMgHljigU4=; h=From:To:Cc:Subject:In-Reply-To:References:Date:Message-ID: MIME-Version:Content-Type; b=riuDsEkUCUAAkF6ld5R7GJzOAZUxEPvoE3X+pIIjOHi9TIVcS+5p6weCqJQNfCpthdLS3K2Vv0b/y9s84wp31IMs/L8GuoIC5X+7rbjH8FLkO1X17jhmXUN+Sh0NUZb83C4R5CFcn7XEFqebLVEvuq9miuDPbHfyJ5lzciEoCYE= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=RWpcAbsW; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="RWpcAbsW" Received: by smtp.kernel.org (Postfix) with ESMTPSA id CF0C2C19423; Mon, 30 Mar 2026 14:57:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1774882638; bh=1gI6dUoAUj8KI/jS+DQQsDNccGUp1WnD6AMgHljigU4=; h=From:To:Cc:Subject:In-Reply-To:References:Date:From; b=RWpcAbsWyohbBNVRI/28hU3kGOyBUH3bs3DIohP/HKwq1n+AOhBTqOKj0lsX36VJY TINZAsardVUEhpNXMUIZrda66iipzfm0Zdgod0VcsNWdr8BXgGLqvK1QqM4xoqUT8U TxhuhCQxEXE4HqAs2Oq29T3S72vrZkLi9zI0UvdSB8b2NUVjmCA4sz9CsSEjoeENUE vA8I3n/O3a0/ZYrv3l1VRofzmBq+/288ppY3G/wepxo8MUlZ88/TNXGpZIOgtR0uRQ 87YLwiEzOpBcIeOZ1j8DsWZTou3EGY324VvfHNArWPyD2nYCoQRjVywLSj8R00OrfX u6nwmcbfXXcdw== From: Pratyush Yadav To: Haoyu Lu Cc: Tudor Ambarus , Pratyush Yadav , Michael Walle , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] mtd: spi-nor: micron-st: Enable die erase support for MT35XU02GCBA In-Reply-To: <20260323114636.2020-1-hechushiguitu666@gmail.com> (Haoyu Lu's message of "Mon, 23 Mar 2026 19:46:35 +0800") References: <20260323114636.2020-1-hechushiguitu666@gmail.com> Date: Mon, 30 Mar 2026 14:57:15 +0000 Message-ID: <2vxz4ilxjrg4.fsf@kernel.org> User-Agent: Gnus/5.13 (Gnus v5.13) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain On Mon, Mar 23 2026, Haoyu Lu wrote: > From: "haoyu.lu" > > The MT35XU02GCBA flash device does not support chip erase according > to its datasheet, but supports die erase. The existing code had a TODO > comment noting that the SPI_NOR_IO_MODE_EN_VOLATILE flag probably needs > to be enabled and the driver implementation needs to be converted to > use die erase. > > This patch enables the SPI_NOR_IO_MODE_EN_VOLATILE flag and adds the > mt35xu01gbba_fixups to the MT35XU02GCBA entry, which includes the > micron_st_nor_two_die_late_init() function that sets up die erase > support. > > With these changes, the flash device can properly use die erase > operations instead of chip erase. > > Signed-off-by: haoyu.lu > --- > drivers/mtd/spi-nor/micron-st.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c > index 88033384a71e..4e8c6ef14697 100644 > --- a/drivers/mtd/spi-nor/micron-st.c > +++ b/drivers/mtd/spi-nor/micron-st.c > @@ -220,7 +220,8 @@ static const struct flash_info micron_nor_parts[] = { > .size = SZ_256M, > .no_sfdp_flags = SECT_4K | SPI_NOR_OCTAL_READ, > .mfr_flags = USE_FSR, Since the TODO comment is now resolved with this patch, please remove it. > - .fixup_flags = SPI_NOR_4B_OPCODES, > + .fixup_flags = SPI_NOR_4B_OPCODES | SPI_NOR_IO_MODE_EN_VOLATILE, > + .fixups = &mt35xu01gbba_fixups, Also, rename mt35xu01gbba_fixups to something like "mt35_two_die_fixups" so the naming isn't confusing. With that, Reviewed-by: Pratyush Yadav > }, > }; -- Regards, Pratyush Yadav