From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D455B411603 for ; Tue, 31 Mar 2026 15:47:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774972065; cv=none; b=D9R7FjWQv5JJM+C9znPw2hrfcJGJfycwB9Nu6FI1OPcyxEw1i0oP+wEbVVpqQ3FcnkJaLZhAcBxIeQ/xDwc94wCqv2OAQ5jFAI6kW/6upGHLnp6b0iLCV1gqHDEPcfilcd0RDbOSRO3KGJM2IkqLm3u8C8sBSil8RCUqOKCQQvk= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774972065; c=relaxed/simple; bh=mBuDfTfKpWYecd6eibKj5laXng98qmkBlzzEIdVW96E=; h=From:To:Cc:Subject:In-Reply-To:References:Date:Message-ID: MIME-Version:Content-Type; b=UIPaMuhneHvS0IfTSjJEviBJWjeDfQusyNVI8E+QvtAaAI2PLKDBCWkEHjasOsPJh98Djxf3m9XDtmjsw5Ja0lc3n1J5M0Ftu7/AmVFbcrOvuqOEzPPu/N0G88hisPiw79o8LSNj3ydUJbVjebN6xMZalST58yj8DQ/JlEFXR0s= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=planXvJX; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="planXvJX" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8206BC19423; Tue, 31 Mar 2026 15:47:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1774972065; bh=mBuDfTfKpWYecd6eibKj5laXng98qmkBlzzEIdVW96E=; h=From:To:Cc:Subject:In-Reply-To:References:Date:From; b=planXvJXlOFswX4ewCUATOalFLYqwyE7p1yvcD9nonS1a8eiFUktJX55jQGAf+Qi1 YdGkt/Nyx79m7e1scxk22OXp8UZolYdufGcnExwaaiJC6TAMQuml9QSV5NscDQvyIt RckgoATXBNWU6U5wrUgX6dcfTw/a5P9HnvjkK5dxC5rtrIoTQR9shFVq0KGKNlhHi1 tyijEsBr0sTmt/3ZAqiueUZZciBHb4xhiVPb6Nnre7dHQ3UH7gDYeYqaYH7UsB/qsM ambxmKe7eJYMrJbkt+5275TrYPqeZfKMGmQ8j22ebEr8kQfu9izZ8i210CxxfcS57w BVTqCBDWpMueQ== From: Pratyush Yadav To: Haoyu Lu Cc: Tudor Ambarus , Pratyush Yadav , Michael Walle , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v3] mtd: spi-nor: micron-st: Enable die erase support for MT35XU02GCBA In-Reply-To: <20260331095354.1861-1-hechushiguitu666@gmail.com> (Haoyu Lu's message of "Tue, 31 Mar 2026 17:53:51 +0800") References: <20260331095354.1861-1-hechushiguitu666@gmail.com> Date: Tue, 31 Mar 2026 15:47:41 +0000 Message-ID: <2vxza4vohug2.fsf@kernel.org> User-Agent: Gnus/5.13 (Gnus v5.13) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain On Tue, Mar 31 2026, Haoyu Lu wrote: > The MT35XU02GCBA flash device does not support chip erase according > to its datasheet, but supports die erase. The existing code had a TODO > comment noting that the SPI_NOR_IO_MODE_EN_VOLATILE flag probably needs > to be enabled and the driver implementation needs to be converted to > use die erase. > > This patch enables the SPI_NOR_IO_MODE_EN_VOLATILE flag and adds the > mt35_two_die_fixups to the MT35XU02GCBA entry, which includes the > micron_st_nor_two_die_late_init() function that sets up die erase > support. > > With these changes, the flash device can properly use die erase > operations instead of chip erase. > > Signed-off-by: Haoyu Lu Applied to spi-nor/next. Thanks! [...] -- Regards, Pratyush Yadav