From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DA9C33CE49B for ; Tue, 31 Mar 2026 07:26:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774941963; cv=none; b=Zf8i/SktqBwsh8gEo0RJ3LHnj7MF4JunIcJPVrWrJvExu7LwD5Y71cQoJm/1Tyj1q5Dd9KWQQ0XR53m1/6QrULamzG9I9RQsu8SY1oz9OKSM/T4irWro/3tNDnmNLluvjqTGlEnhYsVTVq8GXVJchwHAI3+oc8wwUp33xW32kB4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774941963; c=relaxed/simple; bh=J/7X+rQIo5zVinBT3FXkg0ilM9H8ma02sqnI5YAvjc4=; h=From:To:Cc:Subject:In-Reply-To:References:Date:Message-ID: MIME-Version:Content-Type; b=kS9+IL8+dGLHllUfsqZD1qZ5oyLeTsrqZDnypFVDg+G5emdaFQO5hBO6SafHlCK0PT3YFgu9hA4AlKTwUjeuUF8osAkpnjcCF3jLKQKhvBiuBF65yDbXImt1Pj0AWkTenQzXxCRO8no6dlzgzOz9Qtk1czQTrQo2y3snkUFSfUU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=FFDzRNrd; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="FFDzRNrd" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 30204C19423; Tue, 31 Mar 2026 07:26:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1774941962; bh=J/7X+rQIo5zVinBT3FXkg0ilM9H8ma02sqnI5YAvjc4=; h=From:To:Cc:Subject:In-Reply-To:References:Date:From; b=FFDzRNrdpX6MZRGUDWl6u1Wx+lPoS0ARP2Anzjb2OG5UnMjLNIXeEmHbcMs8rfYA1 yb9TrU5ktqKRIGSeNp2muHjjc2zy2iWGCrVbNKGWuoduOL4ePXy/tcNKUnudeH7AOS 8Xn/tNvrkf6rclUDDkGs/dhy2ifIFGF+jhlk+/Zbr1N+mkMhfxiWs0Ua5HO+egBpIt jNK+uN8XbuIHAAUgeBqnijMFKy0I56hhghVdPyJ+46XNumcq/6CGYgT0wODKS3CuJQ FO/k3WKbgtUY+QbiAlgEBlw/IGAk+aY0MVd940IB0WOyVlo/iZHUhO4IvCfjCnx5ft APGeEvHdDmUuQ== From: Pratyush Yadav To: Haoyu Lu Cc: Tudor Ambarus , Pratyush Yadav , Michael Walle , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2] mtd: spi-nor: micron-st: Enable die erase support for MT35XU02GCBA In-Reply-To: <20260331030644.1120-1-hechushiguitu666@gmail.com> (Haoyu Lu's message of "Tue, 31 Mar 2026 11:06:42 +0800") References: <20260331030644.1120-1-hechushiguitu666@gmail.com> Date: Tue, 31 Mar 2026 07:25:58 +0000 Message-ID: <2vxzqzp0iho9.fsf@kernel.org> User-Agent: Gnus/5.13 (Gnus v5.13) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain Hi Haoyu, On Tue, Mar 31 2026, Haoyu Lu wrote: > The MT35XU02GCBA flash device does not support chip erase according > to its datasheet, but supports die erase. The existing code had a TODO > comment noting that the SPI_NOR_IO_MODE_EN_VOLATILE flag probably needs > to be enabled and the driver implementation needs to be converted to > use die erase. > > This patch enables the SPI_NOR_IO_MODE_EN_VOLATILE flag and adds the > mt35_two_die_fixups to the MT35XU02GCBA entry, which includes the > micron_st_nor_two_die_late_init() function that sets up die erase > support. > > With these changes, the flash device can properly use die erase > operations instead of chip erase. > > Signed-off-by: Haoyu Lu I tried applying this patch and it fails to apply. It seems you have sent the v2 on top of your v1 patch. You should do the v2 as a fresh patch on top of spi-nor/next with all the changes, and not a incremental version on top of v1. Please squash your two patches and resend. [...] -- Regards, Pratyush Yadav