From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 41C4C3B6379 for ; Tue, 31 Mar 2026 07:10:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774941017; cv=none; b=RMO2FX2K/3Ru6VwRjeFmdrkqYwGXrmLB3ddHj8S1/4bo7zJEZK99HTQMQuwVHMvtpWBR0GJNBMWMym3H/x6+bMYoa4PkTSwMVR82bFIRfXICfjzZVtVJWJgYvpy1K/47rk8Sr0HSdRbKmJ32dHWNYAw8h95OaAJELYb/8pOScqM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774941017; c=relaxed/simple; bh=RR3CtjKWfDUOb/LevbVt+Lxojt6uAl8U9oM3JXrFdIU=; h=From:To:Cc:Subject:In-Reply-To:References:Date:Message-ID: MIME-Version:Content-Type; b=BFHUrCc6fuPewwrijlYxegacJG0RxBbCdTcaRBWlK01qltU8Y84kYbGyJVZ8VvAS3D/mPy4WZXEac3wk5/LDcPNiD3EBEK15p2/dlGebDUZI+kxGMFFc6KL/82YqfLKR54ndDJ1cBXEUfLHmswoTgfHJ4qqeNpwsyasoX6M2pHw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Y86lVtye; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Y86lVtye" Received: by smtp.kernel.org (Postfix) with ESMTPSA id EFDDFC2BCB0; Tue, 31 Mar 2026 07:10:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1774941016; bh=RR3CtjKWfDUOb/LevbVt+Lxojt6uAl8U9oM3JXrFdIU=; h=From:To:Cc:Subject:In-Reply-To:References:Date:From; b=Y86lVtye1rdWVPwrVEvRH8o1K37HvVjyQirZihw4E0p8DbPAKTKqKZi+G/SSt0AGX nIoKLg1LKnV2HOamHlHXe/xda7hwuWtm9HZDVWKYc6C8AgctlLRx6abA+zXoGDUJDZ VPbzrWNNZzOcLz1dtwBhy1HMMqtA0Fs1C03eFyxlI4hYsQzzRrf0lUJ/jrPdAiwP5i S3aoI4mX3cAh1W0nJOQ7N+ajaVxC+2hiuOH+A60h/scnQiQCU/RB40pGp7z06l6S9v qrWDHjTkqc1EX2teqJgT9CkVw8k5imHZ+LZclfWoGbJUVth1qqGFU5xI/5TuhHuKsb +B5PUlbHHrw5A== From: Pratyush Yadav To: Haoyu Lu Cc: Tudor Ambarus , Pratyush Yadav , Michael Walle , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2] mtd: spi-nor: micron-st: Enable die erase support for MT35XU02GCBA In-Reply-To: <20260331030644.1120-1-hechushiguitu666@gmail.com> (Haoyu Lu's message of "Tue, 31 Mar 2026 11:06:42 +0800") References: <20260331030644.1120-1-hechushiguitu666@gmail.com> Date: Tue, 31 Mar 2026 07:10:13 +0000 Message-ID: <2vxzv7eciiei.fsf@kernel.org> User-Agent: Gnus/5.13 (Gnus v5.13) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain On Tue, Mar 31 2026, Haoyu Lu wrote: > The MT35XU02GCBA flash device does not support chip erase according > to its datasheet, but supports die erase. The existing code had a TODO > comment noting that the SPI_NOR_IO_MODE_EN_VOLATILE flag probably needs > to be enabled and the driver implementation needs to be converted to > use die erase. > > This patch enables the SPI_NOR_IO_MODE_EN_VOLATILE flag and adds the > mt35_two_die_fixups to the MT35XU02GCBA entry, which includes the > micron_st_nor_two_die_late_init() function that sets up die erase > support. > > With these changes, the flash device can properly use die erase > operations instead of chip erase. > > Signed-off-by: Haoyu Lu > --- > v2: Remove TODO comment and rename mt35xu01gbba_fixups to mt35_two_die_fixups per review. > > drivers/mtd/spi-nor/micron-st.c | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c > index 4e8c6ef14697..c22d62545391 100644 > --- a/drivers/mtd/spi-nor/micron-st.c > +++ b/drivers/mtd/spi-nor/micron-st.c > @@ -185,7 +185,7 @@ static const struct spi_nor_fixups mt35xu512aba_fixups = { > .post_sfdp = mt35xu512aba_post_sfdp_fixup, > }; > > -static const struct spi_nor_fixups mt35xu01gbba_fixups = { > +static const struct spi_nor_fixups mt35_two_die_fixups = { > .post_sfdp = mt35xu512aba_post_sfdp_fixup, > .late_init = micron_st_nor_two_die_late_init, > }; > @@ -202,7 +202,7 @@ static const struct flash_info micron_nor_parts[] = { > .id = SNOR_ID(0x2c, 0x5b, 0x1b), > .mfr_flags = USE_FSR, > .fixup_flags = SPI_NOR_IO_MODE_EN_VOLATILE, > - .fixups = &mt35xu01gbba_fixups, > + .fixups = &mt35_two_die_fixups, > }, { > /* > * The MT35XU02GCBA flash device does not support chip erase, > @@ -212,7 +212,6 @@ static const struct flash_info micron_nor_parts[] = { > * MT35XU01GBBA, the SPI_NOR_IO_MODE_EN_VOLATILE flag probably > * needs to be enabled. > * > - * TODO: Fix these and test on real hardware. I meant to drop the whole comment. But no problem, I can do that when applying. Reviewed-by: Pratyush Yadav Thanks for the patch! > */ > .id = SNOR_ID(0x2c, 0x5b, 0x1c), > .name = "mt35xu02g", > @@ -221,7 +220,7 @@ static const struct flash_info micron_nor_parts[] = { > .no_sfdp_flags = SECT_4K | SPI_NOR_OCTAL_READ, > .mfr_flags = USE_FSR, > .fixup_flags = SPI_NOR_4B_OPCODES | SPI_NOR_IO_MODE_EN_VOLATILE, > - .fixups = &mt35xu01gbba_fixups, > + .fixups = &mt35_two_die_fixups, > }, > }; > -- Regards, Pratyush Yadav