From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 64AFC38D6AD for ; Fri, 13 Mar 2026 11:15:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773400519; cv=none; b=ujR5mPAmT5ElVn3SeqZx2mifMWPcfc6CNdSxwFHlSqn/hccYp/ZVTK3ZuiWvJDRW5Rj4HNsQuUDquKMsdGIEQQ8Q3kFbbBmRv+AsFJzwSNc0If+l8It5gOr1OkWMqG+5cAXuTsRI6mPgAZeQ8FwTeXKuZ45633s6tpDdAid6q48= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773400519; c=relaxed/simple; bh=jYuoKNBhuCXL3heQKmgb9WQBJ5DvtrphUrCqIJ0uGqY=; h=From:To:Cc:Subject:In-Reply-To:References:Date:Message-ID: MIME-Version:Content-Type; b=M48OzKAaq5VnwkyJCU0Us2NUcZSeIfVKGeTAo2/gqOaIcW8c21zWtDeuM+GNVbr/+039z6VvQBLwpiryCJQ1MZNSBY6PVVMqyHDQ82IPDom0mVkvSwRZ3v3WaRq5WSNI3aXoinCwTz/VmMpKAqZ1ygaiYBHnuGP0lIDA1x7ab+M= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Ip6AnNJ9; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Ip6AnNJ9" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 55DB0C19424; Fri, 13 Mar 2026 11:15:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1773400519; bh=jYuoKNBhuCXL3heQKmgb9WQBJ5DvtrphUrCqIJ0uGqY=; h=From:To:Cc:Subject:In-Reply-To:References:Date:From; b=Ip6AnNJ9yKRYxbPTdl2EIK3JPESyv4vhf3yOyiF7Gz37C3Jrs/f79o3FN4N99TpNd hjC8wHtvLMnRDaWUv8wBT32FyNjaB6avj+oFRT6MJgEvHuluZ9a3343BrLNpBRFRB/ /FGZww/bXttWAXSmw59XjaFC7Tb6vAPXLuQIRqMJoYiDn2cQCtsiCEaM7Jd6qM3FCm oAPa/Oahs3TDB0HIWkqyX0vR4ONjgY6hWXepRihyDexfuTnKwqNT+k0nhVthSI0K+t ZGX54kwQXPXSyB7LyUy/364+6NrgVfBc9BMBu1jYgzO/Ow0lc3UVqheoDVSjYISEV5 ZzUm6osi4T2nA== From: Pratyush Yadav To: Shiji Yang Cc: linux-mtd@lists.infradead.org, Tudor Ambarus , Pratyush Yadav , Michael Walle , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , linux-kernel@vger.kernel.org Subject: Re: [PATCH] mtd: spi-nor: swp: check SR_TB flag when getting tb_mask In-Reply-To: (Shiji Yang's message of "Wed, 28 Jan 2026 20:42:56 +0800") References: Date: Fri, 13 Mar 2026 11:15:15 +0000 Message-ID: <2vxzzf4cdlq4.fsf@kernel.org> User-Agent: Gnus/5.13 (Gnus v5.13) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain On Wed, Jan 28 2026, Shiji Yang wrote: > When the chip does not support top/bottom block protect, the tb_mask > must be set to 0, otherwise SR1 bit5 will be unexpectedly modified. > > Signed-off-by: Shiji Yang Applied to spi-nor/next. Thanks! [...] -- Regards, Pratyush Yadav