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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-612c8f5d06dsm6945128a12.33.2025.07.22.07.52.25 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 22 Jul 2025 07:52:27 -0700 (PDT) Message-ID: <30442713-2990-490a-b076-93c3cfc3901d@oss.qualcomm.com> Date: Tue, 22 Jul 2025 16:52:24 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 07/17] drm/msm/adreno: Add fenced regwrite support To: Dmitry Baryshkov , Akhil P Oommen Cc: Rob Clark , Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org References: <20250720-ifpc-support-v1-0-9347aa5bcbd6@oss.qualcomm.com> <20250720-ifpc-support-v1-7-9347aa5bcbd6@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=EIMG00ZC c=1 sm=1 tr=0 ts=687fa5be cx=c_pps a=wEM5vcRIz55oU/E2lInRtA==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=EUspDBNiAAAA:8 a=5dKzzWTJmYxMyaayncUA:9 a=QEXdDO2ut3YA:10 a=OIgjcC2v60KrkQgK7BGD:22 X-Proofpoint-ORIG-GUID: rxUe0Tzmvv9ki9k72rV26-yn2GXI2sl3 X-Proofpoint-GUID: rxUe0Tzmvv9ki9k72rV26-yn2GXI2sl3 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzIyMDEyNCBTYWx0ZWRfX8wrMQbzJEt1L /aCGYSh/gxxJ3jQcT9ihc4GubEMGwmLWGnKze69ByT/vAQiYTtSyXSa8/06vEYY1hG2OTTkGHvh sjA3dvxik/HVCqyYxxbRtbtJskGboYx9s3i6bzlR4S1qedu5OffmklyUyxAY2ex6yAo7yXFN/E6 4BKbKkf4cY1BZeIY0OUUZmNQMRl6/boRzv4jMHBhv9YY4xgTpIn/mJYuI3597fjoqnoD2SXbk03 +EqOPZDQB6AYhEwIu72MMNdfC8QHV3XJ4xMBRSQSWyZdDnCIU13BMGnK9lGBLKFV+KscfQ3xlzi Vt8yhanPgZYCtupHG0aJPgFaJ5FaZySp9FonvHAYkzIFJgDDh8MKKFAPF5zDUz49u0/s8z9aCa9 cKHqiCVSlQLZ4sPRU7gf/BBAolS1YAMPm9sFdqPJFvPhfF+zQEDGMBs6Gu1gkHEpH8oZ51k9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-22_02,2025-07-21_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 impostorscore=0 lowpriorityscore=0 bulkscore=0 adultscore=0 priorityscore=1501 mlxlogscore=999 phishscore=0 mlxscore=0 clxscore=1015 suspectscore=0 malwarescore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507220124 On 7/22/25 3:39 PM, Dmitry Baryshkov wrote: > On Sun, Jul 20, 2025 at 05:46:08PM +0530, Akhil P Oommen wrote: >> There are some special registers which are accessible even when GX power >> domain is collapsed during an IFPC sleep. Accessing these registers >> wakes up GPU from power collapse and allow programming these registers >> without additional handshake with GMU. This patch adds support for this >> special register write sequence. >> >> Signed-off-by: Akhil P Oommen >> --- >> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 63 ++++++++++++++++++++++++++++++- >> drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 + >> drivers/gpu/drm/msm/adreno/a6xx_preempt.c | 20 +++++----- >> 3 files changed, 73 insertions(+), 11 deletions(-) >> >> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >> index 491fde0083a202bec7c6b3bca88d0e5a717a6560..8c004fc3abd2896d467a9728b34e99e4ed944dc4 100644 >> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >> @@ -16,6 +16,67 @@ >> >> #define GPU_PAS_ID 13 >> >> +static bool fence_status_check(struct msm_gpu *gpu, u32 offset, u32 value, u32 status, u32 mask) >> +{ >> + /* Success if !writedropped0/1 */ >> + if (!(status & mask)) >> + return true; >> + >> + udelay(10); > > Why do we need udelay() here? Why can't we use interval setting inside > gmu_poll_timeout()? Similarly here: [...] >> + if (!gmu_poll_timeout(gmu, REG_A6XX_GMU_AHB_FENCE_STATUS, status, >> + fence_status_check(gpu, offset, value, status, mask), 0, 1000)) >> + return 0; >> + >> + dev_err_ratelimited(gmu->dev, "delay in fenced register write (0x%x)\n", >> + offset); >> + >> + /* Try again for another 1ms before failing */ >> + gpu_write(gpu, offset, value); >> + if (!gmu_poll_timeout(gmu, REG_A6XX_GMU_AHB_FENCE_STATUS, status, >> + fence_status_check(gpu, offset, value, status, mask), 0, 1000)) >> + return 0; >> + >> + dev_err_ratelimited(gmu->dev, "fenced register write (0x%x) fail\n", >> + offset); We may want to combine the two, so as not to worry the user too much.. If it's going to fail, I would assume it's going to fail both checks (unless e.g. the bus is so congested a single write can't go through to a sleepy GPU across 2 miliseconds, but that's another issue) Konrad