From: Arnd Bergmann <arnd@arndb.de>
To: linux-arm-kernel@lists.infradead.org
Cc: Robert Richter <rric@kernel.org>,
Bjorn Helgaas <bhelgaas@google.com>,
Rob Herring <robh+dt@kernel.org>, Pawel Moll <pawel.moll@arm.com>,
Mark Rutland <mark.rutland@arm.com>,
Ian Campbell <ijc+devicetree@hellion.org.uk>,
Kumar Gala <galak@codeaurora.org>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will.deacon@arm.com>,
devicetree@vger.kernel.org, linux-pci@vger.kernel.org,
Liviu Dudau <liviu.dudau@arm.com>,
linux-kernel@vger.kernel.org,
Robert Richter <rrichter@cavium.com>,
Sunil Goutham <sgoutham@cavium.com>
Subject: Re: [PATCH 3/6] pci, thunder: Add PCIe host controller devicetree bindings
Date: Wed, 24 Sep 2014 18:06:04 +0200 [thread overview]
Message-ID: <3082935.e3X4GsVUDn@wuerfel> (raw)
In-Reply-To: <1411573068-12952-4-git-send-email-rric@kernel.org>
On Wednesday 24 September 2014 17:37:45 Robert Richter wrote:
>
> + pcie0@0x8480,00000000 {
The name should be pci, not pci0.
> + compatible = "cavium,thunder-pcie";
> + device_type = "pci";
> + msi-parent = <&its>;
> + bus-range = <0 255>;
> + #size-cells = <2>;
> + #address-cells = <3>;
> + reg = <0x8480 0x00000000 0 0x10000000>; /* Configuration space */
> + ranges = <0x03000000 0x8010 0x00000000 0x8010 0x00000000 0x70 0x00000000>, /* mem ranges */
> + <0x03000000 0x8300 0x00000000 0x8300 0x00000000 0x80 0x00000000>,
> + <0x03000000 0x87e0 0x00000000 0x87e0 0x00000000 0x01 0x00000000>;
> + };
If you claim the entire 0-255 bus range, I think you should also
specify a domain, otherwise it's not predictable which domain you
get.
The interrupt-map and interrupt-map-mask properties are required for PCI,
otherwise you can't do LSI interrupts.
If your hardware can support it, you should also list I/O space and prefetchable
memory spaces. Can you explain why you have multiple non-prefetchable ranges?
Arnd
next prev parent reply other threads:[~2014-09-24 16:06 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-09-24 15:37 [PATCH 0/6] pci, thunder: Add Cavium Thunder PCIe host controller Robert Richter
2014-09-24 15:37 ` [PATCH 1/6] pci, thunder: Add support for " Robert Richter
2014-09-24 16:12 ` Arnd Bergmann
2014-09-24 16:49 ` Will Deacon
2014-09-30 9:14 ` Sunil Kovvuri
2014-09-24 15:37 ` [PATCH 2/6] GICv3: Add ITS entry to THUNDER dts Robert Richter
2015-06-25 23:19 ` Chalamarla, Tirumalesh
2015-06-26 9:00 ` Marc Zyngier
2014-09-24 15:37 ` [PATCH 3/6] pci, thunder: Add PCIe host controller devicetree bindings Robert Richter
2014-09-24 16:06 ` Arnd Bergmann [this message]
2014-09-24 18:04 ` Sunil Kovvuri
2014-09-24 18:34 ` Arnd Bergmann
2014-09-24 19:07 ` Sunil Kovvuri
2014-09-25 7:31 ` Arnd Bergmann
2014-09-25 16:16 ` Bjorn Helgaas
2014-09-25 19:26 ` Arnd Bergmann
2014-09-25 20:10 ` Bjorn Helgaas
2014-09-25 20:22 ` Arnd Bergmann
2014-09-25 20:49 ` Bjorn Helgaas
2014-09-26 18:26 ` Rob Herring
2014-09-30 9:11 ` Sunil Kovvuri
2014-10-07 14:27 ` Robert Richter
2014-10-07 15:01 ` Liviu Dudau
2014-10-08 8:49 ` Robert Richter
2014-10-08 16:44 ` Liviu Dudau
2014-10-09 6:23 ` Robert Richter
2014-09-24 15:37 ` [PATCH 4/6] pci, thunder: Document " Robert Richter
2014-09-24 15:37 ` [PATCH 5/6] arm64, defconfig: Enable PCI Robert Richter
2014-09-24 16:14 ` Arnd Bergmann
2014-09-24 16:26 ` Robert Richter
2014-09-24 17:10 ` Catalin Marinas
2014-09-24 18:40 ` Arnd Bergmann
2014-09-25 9:35 ` Catalin Marinas
2014-09-25 10:45 ` Arnd Bergmann
2014-09-24 15:37 ` [PATCH 6/6] pci, thunder: Enable Cavium Thunder PCIe host controller Robert Richter
2014-09-24 17:12 ` Catalin Marinas
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