From: Heiko Stuebner <heiko@sntech.de>
To: krzk+dt@kernel.org, palmer@dabbelt.com, robh+dt@kernel.org,
linux-riscv@lists.infradead.org
Cc: conor.dooley@microchip.com, Cyril.Jean@microchip.com,
daire.mcnamara@microchip.com, paul.walmsley@sifive.com,
aou@eecs.berkeley.edu, palmer@rivosinc.com, arnd@arndb.de,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org, Conor Dooley <mail@conchuod.ie>
Subject: Re: [PATCH v3 8/8] riscv: dts: microchip: add the sundance polarberry
Date: Wed, 04 May 2022 01:55:42 +0200 [thread overview]
Message-ID: <3101012.5fSG56mABF@phil> (raw)
In-Reply-To: <20220501192557.2631936-9-mail@conchuod.ie>
Am Sonntag, 1. Mai 2022, 21:25:59 CEST schrieb Conor Dooley:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> Add a minimal device tree for the PolarFire SoC based Sundance
> PolarBerry.
>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
[...]
> diff --git a/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts b/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts
> new file mode 100644
> index 000000000000..96ec589d1571
> --- /dev/null
> +++ b/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts
> @@ -0,0 +1,95 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/* Copyright (c) 2020-2022 Microchip Technology Inc */
> +
> +/dts-v1/;
> +
> +#include "mpfs.dtsi"
> +#include "mpfs-polarberry-fabric.dtsi"
> +
> +/* Clock frequency (in Hz) of the rtcclk */
> +#define MTIMER_FREQ 1000000
> +
> +/ {
> + model = "Sundance PolarBerry";
> + compatible = "sundance,polarberry", "microchip,mpfs";
> +
> + aliases {
> + serial0 = &mmuart0;
> + ethernet0 = &mac1;
I guess you could sort them alphabetically (ethernet above serial0)
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + cpus {
> + timebase-frequency = <MTIMER_FREQ>;
> + };
> +
> + ddrc_cache_lo: memory@80000000 {
> + device_type = "memory";
> + reg = <0x0 0x80000000 0x0 0x2e000000>;
> + status = "okay";
"okay" is implied I think, so when you only add the node
here, you probably don't need to specify the status.
> + };
> +
> + ddrc_cache_hi: memory@1000000000 {
> + device_type = "memory";
> + reg = <0x10 0x00000000 0x0 0xC0000000>;
> + status = "okay";
> + };
> +};
> +
> +&refclk {
> + clock-frequency = <125000000>;
> +};
> +
> +&mmuart0 {
> + status = "okay";
> +};
> +
> +&mmc {
> + status = "okay";
having the status property last (below sd-uhssdr104) can be helpful
for readability, as readers would know where to expect it.
> + bus-width = <4>;
> + disable-wp;
> + cap-sd-highspeed;
> + cap-mmc-highspeed;
> + card-detect-delay = <200>;
> + mmc-ddr-1_8v;
> + mmc-hs200-1_8v;
> + sd-uhs-sdr12;
> + sd-uhs-sdr25;
> + sd-uhs-sdr50;
> + sd-uhs-sdr104;
> +};
> +
> +&mac1 {
> + status = "okay";
> + phy-mode = "sgmii";
> + phy-handle = <&phy1>;
> + phy1: ethernet-phy@5 {
> + reg = <5>;
> + ti,fifo-depth = <0x01>;
> + };
> + phy0: ethernet-phy@4 {
> + reg = <4>;
> + ti,fifo-depth = <0x01>;
> + };
> +};
> +
> +&mac0 {
> + status = "disabled";
mac0 is already disabled in the mpfs.dtsi, so you either don't
need to duplicate it here, or if it's a reminder of something,
I guess a comment for the "why" would be helpful.
> + phy-mode = "sgmii";
> + phy-handle = <&phy0>;
> +};
> +
> +&rtc {
> + status = "okay";
> +};
> +
> +&mbox {
> + status = "okay";
> +};
> +
> +&syscontroller {
> + status = "okay";
> +};
My personal preference would be alphabetical sorting also for
phandles, so
&mac0 {}
&mac1 {}
&mbox {}
&refclk {}
&rtc {}
etc - makes finding things a lot easier in the long run
especially when files get longer.
Heiko
next prev parent reply other threads:[~2022-05-03 23:55 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-01 19:25 [PATCH v3 0/8] PolarFire SoC dt for 5.19 Conor Dooley
2022-05-01 19:25 ` [PATCH v3 1/8] riscv: dts: microchip: remove icicle memory clocks Conor Dooley
2022-05-03 23:29 ` Heiko Stuebner
2022-05-01 19:25 ` [PATCH v3 2/8] riscv: dts: microchip: move sysctrlr out of soc bus Conor Dooley
2022-05-03 23:37 ` Heiko Stuebner
2022-05-04 6:43 ` Conor.Dooley
2022-05-01 19:25 ` [PATCH v3 3/8] riscv: dts: microchip: remove soc vendor from filenames Conor Dooley
2022-05-03 23:39 ` Heiko Stuebner
2022-05-01 19:25 ` [PATCH v3 4/8] dt-bindings: riscv: microchip: document icicle reference design Conor Dooley
2022-05-03 15:27 ` Krzysztof Kozlowski
2022-05-01 19:25 ` [PATCH v3 5/8] riscv: dts: microchip: make the fabric dtsi board specific Conor Dooley
2022-05-03 23:47 ` Heiko Stuebner
2022-05-04 6:48 ` Conor.Dooley
2022-05-04 7:11 ` Heiko Stübner
2022-05-01 19:25 ` [PATCH v3 6/8] dt-bindings: vendor-prefixes: add Sundance DSP Conor Dooley
2022-05-01 19:25 ` [PATCH v3 7/8] dt-bindings: riscv: microchip: add polarberry compatible string Conor Dooley
2022-05-01 19:25 ` [PATCH v3 8/8] riscv: dts: microchip: add the sundance polarberry Conor Dooley
2022-05-03 23:55 ` Heiko Stuebner [this message]
2022-05-04 6:51 ` Conor.Dooley
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