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[78.11.189.27]) by smtp.googlemail.com with ESMTPSA id l26-20020a2e701a000000b002463f024de9sm967013ljc.110.2022.03.18.06.51.35 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 18 Mar 2022 06:51:37 -0700 (PDT) Message-ID: <319cf016-55fb-dcd4-9157-ad795c8e68ff@kernel.org> Date: Fri, 18 Mar 2022 14:51:34 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.5.0 Subject: Re: [PATCH v2 1/2] dt-bindings: phy: mediatek: Add YAML schema for PCIe PHY Content-Language: en-US To: AngeloGioacchino Del Regno , Jianjun Wang , Chunfeng Yun , Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Matthias Brugger , Chen-Yu Tsai Cc: linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, rex-bc.chen@mediatek.com, randy.wu@mediatek.com, jieyy.yang@mediatek.com, chuanjia.liu@mediatek.com, qizhong.cheng@mediatek.com, jian.yang@mediatek.com References: <20220318095417.2016-1-jianjun.wang@mediatek.com> <20220318095417.2016-2-jianjun.wang@mediatek.com> <2e0989c3-7132-6091-5c9e-5dc8d9af22e8@collabora.com> From: Krzysztof Kozlowski In-Reply-To: <2e0989c3-7132-6091-5c9e-5dc8d9af22e8@collabora.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 18/03/2022 12:12, AngeloGioacchino Del Regno wrote: > Il 18/03/22 10:54, Jianjun Wang ha scritto: >> Add YAML schema documentation for PCIe PHY on MediaTek chipsets. >> >> Signed-off-by: Jianjun Wang >> --- >> .../bindings/phy/mediatek,pcie-phy.yaml | 75 +++++++++++++++++++ >> 1 file changed, 75 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml >> >> diff --git a/Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml >> new file mode 100644 >> index 000000000000..868bf976568b >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml >> @@ -0,0 +1,75 @@ >> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/phy/mediatek,pcie-phy.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: MediaTek PCIe PHY >> + >> +maintainers: >> + - Jianjun Wang >> + >> +description: | >> + The PCIe PHY supports physical layer functionality for PCIe Gen3 port. >> + >> +properties: >> + compatible: >> + const: mediatek,mt8195-pcie-phy > > Since I don't expect this driver to be only for MT8195, but to be extended to > support some more future MediaTek SoCs and, depending on the number of differences > in the possible future Gen4 PHYs, even different gen's, I propose to add a generic > compatible as const. > > So you'll have something like: > > - enum: > - mediatek,mt8195-pcie-phy > - const: mediatek,pcie-gen3-phy I am not sure if this is a good idea. How sure are you that there will be no different PCIe Gen3 PHY not compatible with this one? Best regards, Krzysztof