From: Jon Hunter <jonathanh@nvidia.com>
To: Ashish Mhetre <amhetre@nvidia.com>,
will@kernel.org, robin.murphy@arm.com, joro@8bytes.org,
robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
nicolinc@nvidia.com
Cc: thierry.reding@gmail.com, vdumpa@nvidia.com, jgg@ziepe.ca,
linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-tegra@vger.kernel.org
Subject: Re: [PATCH V7 4/4] arm64: dts: nvidia: Add nodes for CMDQV
Date: Wed, 17 Dec 2025 20:42:31 +0000 [thread overview]
Message-ID: <325a9641-a3cb-4137-8cca-99597ca2caa0@nvidia.com> (raw)
In-Reply-To: <20251215064819.3345361-5-amhetre@nvidia.com>
On 15/12/2025 06:48, Ashish Mhetre wrote:
> The Command Queue Virtualization (CMDQV) hardware is part of the
> SMMUv3 implementation on NVIDIA Tegra SoCs. It assists in
> virtualizing the command queue for the SMMU.
>
> Update SMMU compatible strings to use nvidia,tegra264-smmu to enable
> CMDQV support. Add device tree nodes for the CMDQV hardware and enable
> them on the tegra264-p3834 platform where SMMUs are enabled. Each SMMU
> instance is paired with its corresponding CMDQV instance via the
> nvidia,cmdqv property.
>
> Signed-off-by: Ashish Mhetre <amhetre@nvidia.com>
> ---
> .../arm64/boot/dts/nvidia/tegra264-p3834.dtsi | 8 +++
> arch/arm64/boot/dts/nvidia/tegra264.dtsi | 50 +++++++++++++++++--
> 2 files changed, 53 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi b/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi
> index 06795c82427a..7e2c3e66c2ab 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi
> @@ -23,8 +23,16 @@ iommu@5000000 {
> status = "okay";
> };
>
> + cmdqv@5200000 {
> + status = "okay";
> + };
> +
> iommu@6000000 {
> status = "okay";
> };
> +
> + cmdqv@6200000 {
> + status = "okay";
> + };
> };
> };
> diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
> index f137565da804..9eb7058e3149 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
> @@ -3361,7 +3361,7 @@ bus@8100000000 {
> <0x02 0x00000000 0xd0 0x00000000 0x08 0x80000000>; /* ECAM, prefetchable memory, I/O */
>
> smmu1: iommu@5000000 {
> - compatible = "arm,smmu-v3";
> + compatible = "nvidia,tegra264-smmu", "arm,smmu-v3";
> reg = <0x00 0x5000000 0x0 0x200000>;
> interrupts = <GIC_SPI 12 IRQ_TYPE_EDGE_RISING>,
> <GIC_SPI 13 IRQ_TYPE_EDGE_RISING>;
> @@ -3370,10 +3370,18 @@ smmu1: iommu@5000000 {
>
> #iommu-cells = <1>;
> dma-coherent;
> + nvidia,cmdqv = <&cmdqv1>;
> + };
> +
> + cmdqv1: cmdqv@5200000 {
> + compatible = "nvidia,tegra264-cmdqv";
> + reg = <0x00 0x5200000 0x0 0x830000>;
> + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> };
>
> smmu2: iommu@6000000 {
> - compatible = "arm,smmu-v3";
> + compatible = "nvidia,tegra264-smmu", "arm,smmu-v3";
> reg = <0x00 0x6000000 0x0 0x200000>;
> interrupts = <GIC_SPI 1 IRQ_TYPE_EDGE_RISING>,
> <GIC_SPI 2 IRQ_TYPE_EDGE_RISING>;
> @@ -3382,6 +3390,14 @@ smmu2: iommu@6000000 {
>
> #iommu-cells = <1>;
> dma-coherent;
> + nvidia,cmdqv = <&cmdqv2>;
> + };
> +
> + cmdqv2: cmdqv@6200000 {
> + compatible = "nvidia,tegra264-cmdqv";
> + reg = <0x00 0x6200000 0x0 0x830000>;
> + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> };
>
> mc: memory-controller@8020000 {
> @@ -3437,7 +3453,7 @@ emc: external-memory-controller@8800000 {
> };
>
> smmu0: iommu@a000000 {
> - compatible = "arm,smmu-v3";
> + compatible = "nvidia,tegra264-smmu", "arm,smmu-v3";
> reg = <0x00 0xa000000 0x0 0x200000>;
> interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
> <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
> @@ -3446,10 +3462,18 @@ smmu0: iommu@a000000 {
>
> #iommu-cells = <1>;
> dma-coherent;
> + nvidia,cmdqv = <&cmdqv0>;
> + };
> +
> + cmdqv0: cmdqv@a200000 {
> + compatible = "nvidia,tegra264-cmdqv";
> + reg = <0x00 0xa200000 0x0 0x830000>;
> + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> };
>
> smmu4: iommu@b000000 {
> - compatible = "arm,smmu-v3";
> + compatible = "nvidia,tegra264-smmu", "arm,smmu-v3";
> reg = <0x00 0xb000000 0x0 0x200000>;
> interrupts = <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
> <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>;
> @@ -3458,6 +3482,14 @@ smmu4: iommu@b000000 {
>
> #iommu-cells = <1>;
> dma-coherent;
> + nvidia,cmdqv = <&cmdqv4>;
> + };
> +
> + cmdqv4: cmdqv@b200000 {
> + compatible = "nvidia,tegra264-cmdqv";
> + reg = <0x00 0xb200000 0x0 0x830000>;
> + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> };
>
> i2c14: i2c@c410000 {
> @@ -3690,7 +3722,7 @@ bus@8800000000 {
> ranges = <0x00 0x00000000 0x88 0x00000000 0x01 0x00000000>;
>
> smmu3: iommu@6000000 {
> - compatible = "arm,smmu-v3";
> + compatible = "nvidia,tegra264-smmu", "arm,smmu-v3";
> reg = <0x00 0x6000000 0x0 0x200000>;
> interrupts = <GIC_SPI 225 IRQ_TYPE_EDGE_RISING>,
> <GIC_SPI 226 IRQ_TYPE_EDGE_RISING>;
> @@ -3699,6 +3731,14 @@ smmu3: iommu@6000000 {
>
> #iommu-cells = <1>;
> dma-coherent;
> + nvidia,cmdqv = <&cmdqv3>;
> + };
> +
> + cmdqv3: cmdqv@6200000 {
> + compatible = "nvidia,tegra264-cmdqv";
> + reg = <0x00 0x6200000 0x0 0x830000>;
> + interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> };
>
> hda@90b0000 {
Looks good to me.
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Jon
--
nvpublic
prev parent reply other threads:[~2025-12-18 0:09 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-15 6:48 [PATCH V7 0/4] Add device tree support for NVIDIA Tegra CMDQV Ashish Mhetre
2025-12-15 6:48 ` [PATCH V7 1/4] iommu/tegra241-cmdqv: Decouple driver from ACPI Ashish Mhetre
2025-12-15 6:48 ` [PATCH V7 2/4] iommu/arm-smmu-v3: Add device-tree support for CMDQV driver Ashish Mhetre
2025-12-17 20:43 ` Jon Hunter
2025-12-18 6:32 ` Ashish Mhetre
2025-12-18 8:48 ` Jon Hunter
2025-12-18 18:57 ` Nicolin Chen
2025-12-19 10:48 ` Jon Hunter
2025-12-19 18:49 ` Nicolin Chen
2026-01-07 6:44 ` Ashish Mhetre
2026-01-09 9:45 ` Jon Hunter
2026-01-13 5:12 ` Ashish Mhetre
2025-12-15 6:48 ` [PATCH V7 3/4] dt-bindings: iommu: Add NVIDIA Tegra CMDQV support Ashish Mhetre
2025-12-15 21:19 ` Nicolin Chen
2025-12-17 20:31 ` Jon Hunter
2025-12-18 7:03 ` Ashish Mhetre
2026-01-07 6:49 ` Ashish Mhetre
2026-01-09 9:47 ` Jon Hunter
2026-01-13 5:09 ` Ashish Mhetre
2025-12-15 6:48 ` [PATCH V7 4/4] arm64: dts: nvidia: Add nodes for CMDQV Ashish Mhetre
2025-12-15 21:21 ` Nicolin Chen
2025-12-17 20:42 ` Jon Hunter [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=325a9641-a3cb-4137-8cca-99597ca2caa0@nvidia.com \
--to=jonathanh@nvidia.com \
--cc=amhetre@nvidia.com \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=iommu@lists.linux.dev \
--cc=jgg@ziepe.ca \
--cc=joro@8bytes.org \
--cc=krzk+dt@kernel.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-tegra@vger.kernel.org \
--cc=nicolinc@nvidia.com \
--cc=robh@kernel.org \
--cc=robin.murphy@arm.com \
--cc=thierry.reding@gmail.com \
--cc=vdumpa@nvidia.com \
--cc=will@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox