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De Francesco" To: Alison Schofield Cc: Davidlohr Bueso , Jonathan Cameron , Dave Jiang , Vishal Verma , Ira Weiny , Dan Williams , Robert Richter , ming.li@zohomail.com, linux-kernel@vger.kernel.org, linux-cxl@vger.kernel.org Subject: Re: [PATCH 0/4 v3] cxl/core: Enable Region creation on x86 with Low Mem Hole Date: Wed, 26 Mar 2025 17:24:59 +0100 Message-ID: <3287167.Hq7AAxBmiT@fdefranc-mobl3> In-Reply-To: References: <20250314113708.759808-1-fabio.m.de.francesco@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; boundary="nextPart4709506.aCxCBeP46V"; micalg="pgp-sha256"; protocol="application/pgp-signature" --nextPart4709506.aCxCBeP46V Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8"; protected-headers="v1" From: "Fabio M. De Francesco" To: Alison Schofield Date: Wed, 26 Mar 2025 17:24:50 +0100 Message-ID: <3287167.Hq7AAxBmiT@fdefranc-mobl3> In-Reply-To: MIME-Version: 1.0 On Thursday, March 20, 2025 7:10:13=E2=80=AFPM Central European Standard Ti= me Alison Schofield wrote: > On Fri, Mar 14, 2025 at 12:36:29PM +0100, Fabio M. De Francesco wrote: > > The CXL Fixed Memory Window Structure (CFMWS) describes zero or more Ho= st > > Physical Address (HPA) windows that are associated with each CXL Host > > Bridge. Each window represents a contiguous HPA that may be interleaved > > with one or more targets (CXL v3.1 - 9.18.1.3). > >=20 > > The Low Memory Hole (LMH) of x86 is a range of addresses of physical low > > memory to which systems cannot send transactions. On those systems, BIOS > > publishes CFMWS which communicate the active System Physical Address (S= PA) > > ranges that map to a subset of the Host Physical Address (HPA) ranges. = The > > SPA range trims out the hole, and capacity in the endpoint is lost with= no > > SPA to map to CXL HPA in that hole. > >=20 > > In the early stages of CXL Regions construction and attach on platforms > > with Low Memory Holes, the driver fails and returns an error because it > > expects that the CXL Endpoint Decoder range is a subset of the Root > > Decoder's (SPA >=3D HPA). On x86 with LMH's, it happens that SPA < HPA. > >=20 > > Therefore, detect x86 Low Memory Holes, match CXL Root and Endpoint > > Decoders or already made CXL Regions and Decoders to allow the > > construction of new CXL Regions and the attachment of Endpoint Decoders, > > even if SPA < HPA. If needed because of LMH's, adjust the Endpoint Deco= der > > range end to match Root Decoder's. >=20 > Unless dev_dbg() is on, LMH handling won't be apparent. How about adding > a dev_info() that informs the user that a region was adjusted to account > for a LMH. I'm foreseeing looking at logs and divining a LMH, when a > simple log message would be a nice shortcut. >=20 > CXL subsystem is quiet with only 8 dev_info()'s, so if this breaks some > vow of silence, nevermind :) >=20 Yes, sure. It sounds good. Thanks, =46abio --nextPart4709506.aCxCBeP46V Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part. 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