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From: Anshuman Khandual <anshuman.khandual@arm.com>
To: Gavin Shan <gshan@redhat.com>,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org
Cc: catalin.marinas@arm.com, will@kernel.org,
	akpm@linux-foundation.org, maz@kernel.org,
	oliver.upton@linux.dev, ryan.roberts@arm.com, apopple@nvidia.com,
	rananta@google.com, mark.rutland@arm.com, v-songbaohua@oppo.com,
	yangyicong@hisilicon.com, shahuang@redhat.com, yihyu@redhat.com,
	shan.gavin@gmail.com
Subject: Re: [PATCH v3 2/3] arm64: tlb: Improve __TLBI_VADDR_RANGE()
Date: Wed, 10 Apr 2024 13:27:39 +0530	[thread overview]
Message-ID: <32ddd2a6-22c6-49d2-aebb-da5a2e99748d@arm.com> (raw)
In-Reply-To: <20240405035852.1532010-3-gshan@redhat.com>



On 4/5/24 09:28, Gavin Shan wrote:
> The macro returns the operand of TLBI RANGE instruction. A mask needs
> to be applied to each individual field upon producing the operand, to
> avoid the adjacent fields can interfere with each other when invalid
> arguments have been provided. The code looks more tidy at least with
> a mask and FIELD_PREP().
> 
> Suggested-by: Marc Zyngier <maz@kernel.org>
> Signed-off-by: Gavin Shan <gshan@redhat.com>

This looks much better.

Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com>

> ---
>  arch/arm64/include/asm/tlbflush.h | 29 ++++++++++++++++++-----------
>  1 file changed, 18 insertions(+), 11 deletions(-)
> 
> diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h
> index a75de2665d84..243d71f7bc1f 100644
> --- a/arch/arm64/include/asm/tlbflush.h
> +++ b/arch/arm64/include/asm/tlbflush.h
> @@ -142,17 +142,24 @@ static inline unsigned long get_trans_granule(void)
>   * EL1, Inner Shareable".
>   *
>   */
> -#define __TLBI_VADDR_RANGE(baddr, asid, scale, num, ttl)			\
> -	({									\
> -		unsigned long __ta = (baddr);					\
> -		unsigned long __ttl = (ttl >= 1 && ttl <= 3) ? ttl : 0;		\
> -		__ta &= GENMASK_ULL(36, 0);					\
> -		__ta |= __ttl << 37;						\
> -		__ta |= (unsigned long)(num) << 39;				\
> -		__ta |= (unsigned long)(scale) << 44;				\
> -		__ta |= get_trans_granule() << 46;				\
> -		__ta |= (unsigned long)(asid) << 48;				\
> -		__ta;								\
> +#define TLBIR_ASID_MASK		GENMASK_ULL(63, 48)
> +#define TLBIR_TG_MASK		GENMASK_ULL(47, 46)
> +#define TLBIR_SCALE_MASK	GENMASK_ULL(45, 44)
> +#define TLBIR_NUM_MASK		GENMASK_ULL(43, 39)
> +#define TLBIR_TTL_MASK		GENMASK_ULL(38, 37)
> +#define TLBIR_BADDR_MASK	GENMASK_ULL(36,  0)
> +
> +#define __TLBI_VADDR_RANGE(baddr, asid, scale, num, ttl)		\
> +	({								\
> +		unsigned long __ta = 0;					\
> +		unsigned long __ttl = (ttl >= 1 && ttl <= 3) ? ttl : 0;	\
> +		__ta |= FIELD_PREP(TLBIR_BADDR_MASK, baddr);		\
> +		__ta |= FIELD_PREP(TLBIR_TTL_MASK, __ttl);		\
> +		__ta |= FIELD_PREP(TLBIR_NUM_MASK, num);		\
> +		__ta |= FIELD_PREP(TLBIR_SCALE_MASK, scale);		\
> +		__ta |= FIELD_PREP(TLBIR_TG_MASK, get_trans_granule());	\
> +		__ta |= FIELD_PREP(TLBIR_ASID_MASK, asid);		\
> +		__ta;							\
>  	})
>  
>  /* These macros are used by the TLBI RANGE feature. */

  parent reply	other threads:[~2024-04-10  7:57 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-04-05  3:58 [PATCH v3 0/3] arm64: tlb: Fix TLBI RANGE operand Gavin Shan
2024-04-05  3:58 ` [PATCH v3 1/3] " Gavin Shan
2024-04-05 17:10   ` Catalin Marinas
2024-04-08  8:29   ` Ryan Roberts
2024-04-10  8:45     ` Marc Zyngier
2024-04-11  9:59       ` Ryan Roberts
2024-04-10  7:55   ` Anshuman Khandual
2024-04-05  3:58 ` [PATCH v3 2/3] arm64: tlb: Improve __TLBI_VADDR_RANGE() Gavin Shan
2024-04-05 17:10   ` Catalin Marinas
2024-04-08  8:31   ` Ryan Roberts
2024-04-10  7:57   ` Anshuman Khandual [this message]
2024-04-05  3:58 ` [PATCH v3 3/3] arm64: tlb: Allow range operation for MAX_TLBI_RANGE_PAGES Gavin Shan
2024-04-05 17:12   ` Catalin Marinas
2024-04-08  8:43   ` Ryan Roberts
2024-04-10  8:50     ` Marc Zyngier
2024-04-11 10:44       ` Will Deacon
2024-04-10  7:58   ` Anshuman Khandual
2024-04-10  8:43 ` [PATCH v3 0/3] arm64: tlb: Fix TLBI RANGE operand Shaoqin Huang
2024-04-10 17:52 ` (subset) " Catalin Marinas
2024-04-12 16:06 ` Will Deacon

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