From: "Fabio M. De Francesco" <fabio.m.de.francesco@linux.intel.com>
To: Alison Schofield <alison.schofield@intel.com>,
Alison Schofield <alison.schofield@intel.com>
Cc: Davidlohr Bueso <dave@stgolabs.net>,
Jonathan Cameron <jonathan.cameron@huawei.com>,
Dave Jiang <dave.jiang@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>,
Ira Weiny <ira.weiny@intel.com>,
Dan Williams <dan.j.williams@intel.com>,
Robert Richter <rrichter@amd.com>,
ming.li@zohomail.com, linux-kernel@vger.kernel.org,
linux-cxl@vger.kernel.org, Davidlohr Bueso <dave@stgolabs.net>,
Jonathan Cameron <jonathan.cameron@huawei.com>,
Dave Jiang <dave.jiang@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>,
Ira Weiny <ira.weiny@intel.com>,
Dan Williams <dan.j.williams@intel.com>,
Robert Richter <rrichter@amd.com>,
ming.li@zohomail.com, linux-kernel@vger.kernel.org,
linux-cxl@vger.kernel.org
Subject: Re: [PATCH 0/4 v3] cxl/core: Enable Region creation on x86 with Low Mem Hole
Date: Wed, 26 Mar 2025 17:23:21 +0100 [thread overview]
Message-ID: <3304445.h6RI2rZIcs@fdefranc-mobl3> (raw)
In-Reply-To: <Z9tzZkn1rqd2Uk_6@aschofie-mobl2.lan>
On Thursday, March 20, 2025 2:46:14 AM Central European Standard Time Alison Schofield wrote:
> On Fri, Mar 14, 2025 at 12:36:29PM +0100, Fabio M. De Francesco wrote:
> > The CXL Fixed Memory Window Structure (CFMWS) describes zero or more Host
> > Physical Address (HPA) windows that are associated with each CXL Host
> > Bridge. Each window represents a contiguous HPA that may be interleaved
> > with one or more targets (CXL v3.1 - 9.18.1.3).
> >
> > The Low Memory Hole (LMH) of x86 is a range of addresses of physical low
> > memory to which systems cannot send transactions. On those systems, BIOS
> > publishes CFMWS which communicate the active System Physical Address (SPA)
> > ranges that map to a subset of the Host Physical Address (HPA) ranges. The
> > SPA range trims out the hole, and capacity in the endpoint is lost with no
> > SPA to map to CXL HPA in that hole.
> >
> > In the early stages of CXL Regions construction and attach on platforms
> > with Low Memory Holes, the driver fails and returns an error because it
> > expects that the CXL Endpoint Decoder range is a subset of the Root
> > Decoder's (SPA >= HPA). On x86 with LMH's, it happens that SPA < HPA.
> >
> > Therefore, detect x86 Low Memory Holes, match CXL Root and Endpoint
> > Decoders or already made CXL Regions and Decoders to allow the
> > construction of new CXL Regions and the attachment of Endpoint Decoders,
> > even if SPA < HPA. If needed because of LMH's, adjust the Endpoint Decoder
> > range end to match Root Decoder's.
>
> I think the dpa_res field of the endpoint decoder needs adjusting.
> After the region is setup, the cxled->dpa_res has the unadjusted value
> and that leads to region warning and address translation failure because
> the driver 'thinks' that DPA is within a region, but when it tries
> to translate to an HPA in that region, it fails.
>
> Here's where I looked at it: using the cxl-test LMH auto-region (nice!)
> each endpoint decoder is programmed to contribute 512MB to the 1024MB region.
> The LMH adjustment shrunk the region to 768MB, so each endpoint is only
> contributing 384MB to the region.
>
> DPA->HPA address translations of DPA addresses in the 384->512 gap cause
> a problem. The driver will needlessly warn that they are in a region for
> any poison inject or clear, and will fail address translations for any
> poison, general media or dram event.
>
> I think this should fail in region.c: __cxl_dpa_to_region()
> if (dpa > cxled->dpa_res->end || dpa < cxled->dpa_res->start)
> return 0;
>
> For that to fail, LMH code needs to adjust cxled->dpa_res too.
>
>
> To test is using clear_poison you can:
> # echo 536866816 > /sys/kernel/debug/cxl/mem1/clear_poison
> (536866816 = 512MB - 4096)
>
> [ ] cxl_core:__cxl_dpa_to_region:2860: cxl decoder18.0: dpa:0x1ffff000 mapped in region:region0
> [ ] cxl_core:cxl_dpa_to_hpa:2963: cxl_region region0: Addr trans fail: hpa 0x3ff04fffe000 not in region
>
>
> snip
> >
>
Alison,
I'll adjust cxled->dpa_res too.
Thank you for noticing this issue.
Fabio
next prev parent reply other threads:[~2025-03-26 16:23 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-14 11:36 [PATCH 0/4 v3] cxl/core: Enable Region creation on x86 with Low Mem Hole Fabio M. De Francesco
2025-03-14 11:36 ` [PATCH 1/4 v3] cxl/core: Change match_*_by_range() calling convention Fabio M. De Francesco
2025-03-21 15:43 ` Dave Jiang
2025-03-14 11:36 ` [PATCH 2/4 v3] cxl/core: Add helpers to detect Low memory Holes on x86 Fabio M. De Francesco
2025-03-18 15:15 ` Ira Weiny
2025-03-21 10:21 ` Robert Richter
2025-03-26 16:47 ` Fabio M. De Francesco
2025-03-28 10:26 ` Robert Richter
2025-03-28 23:40 ` Dan Williams
2025-03-29 10:05 ` Fabio M. De Francesco
2025-03-14 11:36 ` [PATCH 3/4 v3] cxl/core: Enable Region creation on x86 with Low Memory Hole Fabio M. De Francesco
2025-03-18 20:35 ` Ira Weiny
2025-03-21 10:29 ` Robert Richter
2025-03-14 11:36 ` [PATCH 4/4 v3] cxl/test: Simulate an x86 Low Memory Hole for tests Fabio M. De Francesco
2025-03-18 21:16 ` Ira Weiny
2025-03-21 10:42 ` Robert Richter
2025-03-26 16:58 ` Fabio M. De Francesco
2025-03-28 10:52 ` Robert Richter
2025-03-28 23:40 ` Dan Williams
2025-03-29 10:16 ` Fabio M. De Francesco
2025-03-29 22:01 ` Fabio M. De Francesco
2025-04-03 4:00 ` Dan Williams
2025-03-20 1:46 ` [PATCH 0/4 v3] cxl/core: Enable Region creation on x86 with Low Mem Hole Alison Schofield
2025-03-26 16:23 ` Fabio M. De Francesco [this message]
2025-03-20 18:10 ` Alison Schofield
2025-03-26 16:24 ` Fabio M. De Francesco
2025-03-21 10:34 ` Robert Richter
2025-03-25 16:13 ` Fabio M. De Francesco
2025-03-28 9:02 ` Robert Richter
2025-03-28 21:10 ` Dave Jiang
2025-04-02 11:51 ` Robert Richter
2025-04-02 15:31 ` Dave Jiang
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