From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.7 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7802AC31E44 for ; Fri, 14 Jun 2019 09:52:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 57CB5208CA for ; Fri, 14 Jun 2019 09:52:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727244AbfFNJwb (ORCPT ); Fri, 14 Jun 2019 05:52:31 -0400 Received: from gloria.sntech.de ([185.11.138.130]:38468 "EHLO gloria.sntech.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726900AbfFNJwb (ORCPT ); Fri, 14 Jun 2019 05:52:31 -0400 Received: from we0305.dip.tu-dresden.de ([141.76.177.49] helo=phil.localnet) by gloria.sntech.de with esmtpsa (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.89) (envelope-from ) id 1hbisk-0004H9-GQ; Fri, 14 Jun 2019 11:52:26 +0200 From: Heiko Stuebner To: Jianqun Xu Cc: mark.rutland@arm.com, robh+dt@kernel.org, zhangzj@rock-chips.com, manivannan.sadhasivam@linaro.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH v3 1/1] arm64: dts: rockchip: add core dtsi file for RK3399Pro SoCs Date: Fri, 14 Jun 2019 11:52:25 +0200 Message-ID: <3309819.J5kelTtX6q@phil> In-Reply-To: <20190530000848.28106-1-jay.xu@rock-chips.com> References: <20190529074752.19388-1-jay.xu@rock-chips.com> <20190530000848.28106-1-jay.xu@rock-chips.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Jianqun, Am Donnerstag, 30. Mai 2019, 02:08:48 CEST schrieb Jianqun Xu: > This patch adds core dtsi file for Rockchip RK3399Pro SoCs, > include rk3399.dtsi. Also enable pciei0/pcie_phy for AP to > talk to NPU part inside SoC. > > Signed-off-by: Jianqun Xu could you add the necessary pinctrl entry, as suggested by Manivannan? Thanks Heiko > --- > changes since v2: > - only enable pcie0 and pcie_phy nodes, thanks for Heiko and manivannan > > changes since v1: > - remove dfi and dmc > > arch/arm64/boot/dts/rockchip/rk3399pro.dtsi | 22 +++++++++++++++++++++ > 1 file changed, 22 insertions(+) > create mode 100644 arch/arm64/boot/dts/rockchip/rk3399pro.dtsi > > diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi b/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi > new file mode 100644 > index 000000000000..bb5ebf6608b9 > --- /dev/null > +++ b/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi > @@ -0,0 +1,22 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +// Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd. > + > +#include "rk3399.dtsi" > + > +/ { > + compatible = "rockchip,rk3399pro"; > +}; > + > +/* Default to enabled since AP talk to NPU part over pcie */ > +&pcie_phy { > + status = "okay"; > +}; > + > +/* Default to enabled since AP talk to NPU part over pcie */ > +&pcie0 { > + ep-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; > + num-lanes = <4>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pcie_clkreqn_cpm>; > + status = "okay"; > +}; >