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This clock signal is used as an input > MCLK clock for cameras. >=20 > Unlike later Tegra SoCs, the Tegra 20 can change its CSUS parent, which i= s > why csus_mux is added in a similar way to how CDEV1 and CDEV2 are handled= . >=20 > Signed-off-by: Svyatoslav Ryhel > --- > drivers/clk/tegra/clk-tegra114.c | 7 ++++++- > drivers/clk/tegra/clk-tegra20.c | 20 +++++++++++++------- > drivers/clk/tegra/clk-tegra30.c | 7 ++++++- > 3 files changed, 25 insertions(+), 9 deletions(-) >=20 > diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-teg= ra114.c > index 186b0b81c1ec..00282b0d3763 100644 > --- a/drivers/clk/tegra/clk-tegra114.c > +++ b/drivers/clk/tegra/clk-tegra114.c > @@ -691,7 +691,6 @@ static struct tegra_clk tegra114_clks[tegra_clk_max] = __initdata =3D { > [tegra_clk_tsec] =3D { .dt_id =3D TEGRA114_CLK_TSEC, .present =3D true = }, > [tegra_clk_xusb_host] =3D { .dt_id =3D TEGRA114_CLK_XUSB_HOST, .present= =3D true }, > [tegra_clk_msenc] =3D { .dt_id =3D TEGRA114_CLK_MSENC, .present =3D tru= e }, > - [tegra_clk_csus] =3D { .dt_id =3D TEGRA114_CLK_CSUS, .present =3D true = }, > [tegra_clk_mselect] =3D { .dt_id =3D TEGRA114_CLK_MSELECT, .present =3D= true }, > [tegra_clk_tsensor] =3D { .dt_id =3D TEGRA114_CLK_TSENSOR, .present =3D= true }, > [tegra_clk_i2s3] =3D { .dt_id =3D TEGRA114_CLK_I2S3, .present =3D true = }, > @@ -1047,6 +1046,12 @@ static __init void tegra114_periph_clk_init(void _= _iomem *clk_base, > 0, 82, periph_clk_enb_refcnt); > clks[TEGRA114_CLK_DSIB] =3D clk; > =20 > + /* csus */ > + clk =3D tegra_clk_register_periph_gate("csus", "vi_sensor", 0, > + clk_base, 0, TEGRA114_CLK_CSUS, > + periph_clk_enb_refcnt); > + clks[TEGRA114_CLK_CSUS] =3D clk; > + > /* emc mux */ > clk =3D clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm, > ARRAY_SIZE(mux_pllmcp_clkm), > diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegr= a20.c > index 2c58ce25af75..d8d5afeb6f9b 100644 > --- a/drivers/clk/tegra/clk-tegra20.c > +++ b/drivers/clk/tegra/clk-tegra20.c > @@ -530,7 +530,6 @@ static struct tegra_clk tegra20_clks[tegra_clk_max] _= _initdata =3D { > [tegra_clk_rtc] =3D { .dt_id =3D TEGRA20_CLK_RTC, .present =3D true }, > [tegra_clk_timer] =3D { .dt_id =3D TEGRA20_CLK_TIMER, .present =3D true= }, > [tegra_clk_kbc] =3D { .dt_id =3D TEGRA20_CLK_KBC, .present =3D true }, > - [tegra_clk_csus] =3D { .dt_id =3D TEGRA20_CLK_CSUS, .present =3D true }= , > [tegra_clk_vcp] =3D { .dt_id =3D TEGRA20_CLK_VCP, .present =3D true }, > [tegra_clk_bsea] =3D { .dt_id =3D TEGRA20_CLK_BSEA, .present =3D true }= , > [tegra_clk_bsev] =3D { .dt_id =3D TEGRA20_CLK_BSEV, .present =3D true }= , > @@ -834,6 +833,12 @@ static void __init tegra20_periph_clk_init(void) > clk_base, 0, 93, periph_clk_enb_refcnt); > clks[TEGRA20_CLK_CDEV2] =3D clk; > =20 > + /* csus */ > + clk =3D tegra_clk_register_periph_gate("csus", "csus_mux", 0, > + clk_base, 0, TEGRA20_CLK_CSUS, > + periph_clk_enb_refcnt); > + clks[TEGRA20_CLK_CSUS] =3D clk; > + > for (i =3D 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) { > data =3D &tegra_periph_clk_list[i]; > clk =3D tegra_clk_register_periph_data(clk_base, data); > @@ -1093,14 +1098,15 @@ static struct clk *tegra20_clk_src_onecell_get(st= ruct of_phandle_args *clkspec, > hw =3D __clk_get_hw(clk); > =20 > /* > - * Tegra20 CDEV1 and CDEV2 clocks are a bit special case, their parent > - * clock is created by the pinctrl driver. It is possible for clk user > - * to request these clocks before pinctrl driver got probed and hence > - * user will get an orphaned clock. That might be undesirable because > - * user may expect parent clock to be enabled by the child. > + * Tegra20 CDEV1, CDEV2 and CSUS clocks are a bit special case, their > + * parent clock is created by the pinctrl driver. It is possible for > + * clk user to request these clocks before pinctrl driver got probed > + * and hence user will get an orphaned clock. That might be undesirable > + * because user may expect parent clock to be enabled by the child. > */ > if (clkspec->args[0] =3D=3D TEGRA20_CLK_CDEV1 || > - clkspec->args[0] =3D=3D TEGRA20_CLK_CDEV2) { > + clkspec->args[0] =3D=3D TEGRA20_CLK_CDEV2 || > + clkspec->args[0] =3D=3D TEGRA20_CLK_CSUS) { > parent_hw =3D clk_hw_get_parent(hw); > if (!parent_hw) > return ERR_PTR(-EPROBE_DEFER); > diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegr= a30.c > index 82a8cb9545eb..ca367184e185 100644 > --- a/drivers/clk/tegra/clk-tegra30.c > +++ b/drivers/clk/tegra/clk-tegra30.c > @@ -779,7 +779,6 @@ static struct tegra_clk tegra30_clks[tegra_clk_max] _= _initdata =3D { > [tegra_clk_rtc] =3D { .dt_id =3D TEGRA30_CLK_RTC, .present =3D true }, > [tegra_clk_timer] =3D { .dt_id =3D TEGRA30_CLK_TIMER, .present =3D true= }, > [tegra_clk_kbc] =3D { .dt_id =3D TEGRA30_CLK_KBC, .present =3D true }, > - [tegra_clk_csus] =3D { .dt_id =3D TEGRA30_CLK_CSUS, .present =3D true }= , > [tegra_clk_vcp] =3D { .dt_id =3D TEGRA30_CLK_VCP, .present =3D true }, > [tegra_clk_bsea] =3D { .dt_id =3D TEGRA30_CLK_BSEA, .present =3D true }= , > [tegra_clk_bsev] =3D { .dt_id =3D TEGRA30_CLK_BSEV, .present =3D true }= , > @@ -1008,6 +1007,12 @@ static void __init tegra30_periph_clk_init(void) > 0, 48, periph_clk_enb_refcnt); > clks[TEGRA30_CLK_DSIA] =3D clk; > =20 > + /* csus */ > + clk =3D tegra_clk_register_periph_gate("csus", "vi_sensor", 0, > + clk_base, 0, TEGRA30_CLK_CSUS, > + periph_clk_enb_refcnt); > + clks[TEGRA30_CLK_CSUS] =3D clk; > + > /* pcie */ > clk =3D tegra_clk_register_periph_gate("pcie", "clk_m", 0, clk_base, 0, > 70, periph_clk_enb_refcnt); >=20 Reviewed-by: Mikko Perttunen