Re: [PATCH 00/25] serial: sh-sci: Add external clock and BRG Support

Laurent Pinchart
2015-11-20T08:58:06Z

Hi Geert,

On Friday 20 November 2015 09:22:16 Geert Uytterhoeven wrote:
> On Thu, Nov 19, 2015 at 10:08 PM, Laurent Pinchart wrote:
> > For patches 3-6, 13, 15-16 and 22 and 24,
> >
> > Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
>
> Many thanks for your review comments!

You're welcome.

> > I'm not sure I'd bother with patch 25/25, but I'm not against merging it
> > either. I'd be surprised if the serial driver still worked at all on SH
> > :-)
>
> It should not cause problems, as long as sh7734 doesn't add the optional
> clocks ;-)

To be clear I don't expect this patch set to break it, I expect it to be
broken already :-)

> > On Thursday 19 November 2015 19:38:39 Geert Uytterhoeven wrote:
> >> This patch series adds support to the Renesas SCI serial driver for
> >>
> >> - the optional external clock on (H)SCI(F) and some SCIFA, where this
> >>
> >> pin can serve as a clock input,
> >>
> >> - the optional clock sources for the Baud Rate Generator for External
> >>
> >> Clock (BRG), as found on some SCIF variants and on HSCIF.
> >
> > Could you briefly explain (and even better in a source code comment) how
> > you handle baud rate calculation with the chained BRGs ?
>
> I'll do that. Note that there's no chaining of BRGs, only muxing (so yes, it
> needs more clarification ;-).

Really ? I thought the BRG-EC was one possible input for the internal BRG ?
Does it bypass the internal BRG ? Or do you configure the internal BRG to not
divide the clock when using the BRG-EC ?

> There can be 4 possible sources for the sampling clock:
> 1. Internal BRG (BRR register),
> 2. (H)SCK,
> 3. BRG for external clock
> a. Using SCIF_CLK,
> b. Using the bus clock.

--
Regards,

Laurent Pinchart