From: Marc Zyngier <maz@kernel.org>
To: John Garry <john.garry@huawei.com>
Cc: linux-kernel@vger.kernel.org,
Thomas Gleixner <tglx@linutronix.de>,
Jason Cooper <jason@lakedaemon.net>,
Ming Lei <ming.lei@redhat.com>,
chenxiang <chenxiang66@hisilicon.com>,
Zhou Wang <wangzhou1@hisilicon.com>
Subject: Re: [PATCH v2] irqchip/gic-v3-its: Balance initial LPI affinity across CPUs
Date: Thu, 12 Mar 2020 15:56:14 +0000 [thread overview]
Message-ID: <33bc00d1ba25d5fd53de2413c831d723@kernel.org> (raw)
In-Reply-To: <d23436b5-a207-91e9-be11-f5d0e44b6e12@huawei.com>
Hi John,
On 2020-03-12 15:41, John Garry wrote:
> On 12/03/2020 11:55, Marc Zyngier wrote:
>
> Hi Marc,
>
>> When mapping a LPI, the ITS driver picks the first possible
>> affinity, which is in most cases CPU0, assuming that if
>> that's not suitable, someone will come and set the affinity
>> to something more interesting.
>>
>> It apparently isn't the case, and people complain of poor
>> performance when many interrupts are glued to the same CPU.
>> So let's place the interrupts by finding the "least loaded"
>> CPU (that is, the one that has the fewer LPIs mapped to it).
>> So called 'managed' interrupts are an interesting case where
>> the affinity is actually dictated by the kernel itself, and
>> we should honor this.
>>
>> Reported-by: John Garry <john.garry@huawei.com>
>> Link:
>> https://lore.kernel.org/r/1575642904-58295-1-git-send-email-john.garry@huawei.com
>> Signed-off-by: Marc Zyngier <maz@kernel.org>
>> Cc: John Garry <john.garry@huawei.com>
>> Cc: Ming Lei <ming.lei@redhat.com>
>> ---
>> Reviving this at John's request.
>
> Thanks very much. I may request a colleague test this due to possible
> precautionary office closure.
Huh. Not great... :-(
>
> The major change is that the
>> affinity follows the x86 model, as described by Thomas.
>
> There seems to be a subtle difference between this implementation and
> what Thomas described for managed interrupts handling on x86. That
> being, managed interrupt loading is counted separately to total
> interrupts per CPU for x86. That seems quite important so that we
> spread managed interrupts evenly.
Hmmm. Yes. That'd require a separate per-CPU counter. Nothing too
invasive
though. I'll roll that in soon. I still wonder about interaction of
collocated
managed and non-managed interrupts, but we can cross that bridge later.
>> I expect this to have an impact on platforms like D05, where
>> the SAS driver cannot use managed affinity just yet.
>
> I need some blk-mq and SCSI changes to go in first to improve the
> interrupt handling there, hopefully we can make progress on that soon.
That'd be good.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
next prev parent reply other threads:[~2020-03-12 15:56 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-12 11:55 [PATCH v2] irqchip/gic-v3-its: Balance initial LPI affinity across CPUs Marc Zyngier
2020-03-12 15:41 ` John Garry
2020-03-12 15:56 ` Marc Zyngier [this message]
2020-03-12 16:27 ` John Garry
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