From: "Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>
To: Shravan Ramani <shravankr@nvidia.com>
Cc: Hans de Goede <hdegoede@redhat.com>,
Vadim Pasternak <vadimp@nvidia.com>,
David Thompson <davthompson@nvidia.com>,
"platform-driver-x86@vger.kernel.org"
<platform-driver-x86@vger.kernel.org>,
LKML <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2 2/4] platform/mellanox: mlxbf-pmc: Add support for 64-bit counters and cycle count
Date: Tue, 11 Jun 2024 10:14:59 +0300 (EEST) [thread overview]
Message-ID: <33f25d4f-386c-6df6-344d-8b7aa011e69c@linux.intel.com> (raw)
In-Reply-To: <DM4PR12MB513695D2BE98AA46A95B4C60C0FF2@DM4PR12MB5136.namprd12.prod.outlook.com>
On Mon, 3 Jun 2024, Shravan Ramani wrote:
> > > Both these features are supported by BlueField-3 PMC hardware, hence
> > > the required bit-fields are exposed by the driver via sysfs to allow
> > > the user to configure as needed.
> >
> > I'm trying to understand what happens for the other counter, when the
> > use_odd_counter is enabled? This change also doesn't add code that would
> > make the other counter -EBUSY, should that be done?
>
> When 2 32-bit counters are coupled to form a 64-bit counter using this setting,
> one counter will hold the lower 32 bits while the other will hold the upper 32.
> So the other counter (or syses corresponding to it) also needs to be accessed.
>
> > For 64-bit counter, I suppose the userspace is expected to read the full
> > counter from two sysfs files and combine the value (your documentation
> > doesn't explain this)? That seems non-optimal, why cannot kernel just
> > return the full combined 64-value directly in kernel?
>
> I will add more clear comments for this.
> While it is true that the driver could combine the 2 fields and present a
> 64-bit value via one of the sysfs, the reason for the current approach is that
> there are other interfaces which expose the same counters for our platform
> and there are tools that are expected to work on top of both interfaces for
> the purpose of collecting performance stats.
> The other interfaces follow this
> approach of having lower and upper 32-bits separately in each counter, and
> the tools expect the same. Hence the driver follows this approach to keep
> things consistent across the BlueField platform.
Hi,
I went to look through the existing arrays in mlxbf-pmc.c but did not find
any entries that would have clearly indicated the counters being hi/lo
parts of the same counter. There were a few 0/1 ones which could be the
same counter although I suspect even they are not parts of the same
counter but two separate entities called 0 and 1 having the same counter.
Could you please elaborate further what you meant with the note about
other interfaces above so I can better assess the claim?
--
i.
next prev parent reply other threads:[~2024-06-11 7:16 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-20 11:56 [PATCH v2 0/4] Updates to mlxbf-pmc Shravan Kumar Ramani
2024-05-20 11:56 ` [PATCH v2 1/4] Documentation/ABI: Add document for Mellanox PMC driver Shravan Kumar Ramani
2024-05-27 10:33 ` Ilpo Järvinen
2024-05-20 11:56 ` [PATCH v2 2/4] platform/mellanox: mlxbf-pmc: Add support for 64-bit counters and cycle count Shravan Kumar Ramani
2024-05-27 11:39 ` Ilpo Järvinen
2024-06-03 10:29 ` Shravan Ramani
2024-06-11 7:14 ` Ilpo Järvinen [this message]
2024-06-11 13:34 ` Shravan Ramani
2024-06-12 7:28 ` Ilpo Järvinen
2024-06-14 10:46 ` Shravan Ramani
2024-06-14 10:58 ` Ilpo Järvinen
2024-05-20 11:56 ` [PATCH v2 3/4] platform/mellanox: mlxbf-pmc: Add support for clock_measure performance block Shravan Kumar Ramani
2024-05-20 11:56 ` [PATCH v2 4/4] Documentation/ABI: Add new sysfs fields to sysfs-platform-mellanox-pmc Shravan Kumar Ramani
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