RE: "Verifying and Optimizing Compact NUMA-Aware Locks on Weak Memory Models"

[Jonas Oberhauser <jonas.oberhauser@huawei.com>]

Hi Joel,

> I wonder if this sort of liveness guarantee (or lack thereof) is really a problem in practice, where writes will eventually propagate even though they may not for a bit. Is it possible to write a liveness test case on any hardware, or is this more in the realms of theory?
Either way, quite intriguing!

As I tried to explain before, this problem has nothing to do with stores propagating within a given time to another core. Rather it is due to two stores to the same location happening in a surprising order. I.e., both stores propagate quickly to other cores, but in a surprising coherence order.And if a wmb in the code is replaced by an mb, then this co will create a pb cycle and become forbidden.

Therefore this hang should be observable on a hypothetical LKMM processor which makes use of all the relaxed liberty the LKMM allows. However according to the authors of that paper (who are my colleagues but I haven't been involved deeply in that work), not even Power+gcc allow this reordering to happen, and if that's true it is probably because the wmb is mapped to lwsync which is fully cumulative in Power but not in LKMM.

Best wishes and hope this clears it up, jonas