From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752045AbdBEJmY (ORCPT ); Sun, 5 Feb 2017 04:42:24 -0500 Received: from gloria.sntech.de ([95.129.55.99]:36706 "EHLO gloria.sntech.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751774AbdBEJmW (ORCPT ); Sun, 5 Feb 2017 04:42:22 -0500 From: Heiko Stuebner To: Frank Wang Cc: johnyoun@synopsys.com, gregkh@linuxfoundation.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, linux-rockchip@lists.infradead.org, huangtao@rock-chips.com, kever.yang@rock-chips.com, william.wu@rock-chips.com Subject: Re: [RESEND PATCH 0/1] add multiple clock handling for dwc2 driver Date: Sun, 05 Feb 2017 10:41:23 +0100 Message-ID: <3508420.z4eX5F6ytJ@phil> User-Agent: KMail/5.2.3 (Linux/4.9.0-1-amd64; KDE/5.27.0; x86_64; ; ) In-Reply-To: <1486263061-10681-1-git-send-email-frank.wang@rock-chips.com> References: <1486263061-10681-1-git-send-email-frank.wang@rock-chips.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Frank, Am Sonntag, 5. Februar 2017, 10:51:00 CET schrieb Frank Wang: > The original posting on Jan 19th have not received any responses, so I > resend them. > > The Current default dwc2 just handle one clock named otg, however, it may > have two or more clock need to manage for some new SoCs(such as RK3328), so > this adds change clk to clk's array of dwc2_hsotg to handle more clocks > operation. can you please give a bit more detail on the specific layout. I guess you're talking about hclk_otg_pmu, right? What component does it supply, because I didn't find anything in the partial TRM in the PMU section relating to the "otg". This meant to make sure, you're actually controlling some part of the dwc2 with that second/third/... clock and not some separate component. Heiko