From: "Luck, Tony" <tony.luck@intel.com>
To: Thomas Gleixner <tglx@linutronix.de>, Borislav Petkov <bp@alien8.de>
Cc: "Yu, Fenghua" <fenghua.yu@intel.com>,
linux-kernel <linux-kernel@vger.kernel.org>, x86 <x86@kernel.org>,
"iommu@lists.linux-foundation.org"
<iommu@lists.linux-foundation.org>,
"Ingo Molnar" <mingo@redhat.com>, H Peter Anvin <hpa@zytor.com>,
Andy Lutomirski <luto@kernel.org>,
Jean-Philippe Brucker <jean-philippe@linaro.org>,
Christoph Hellwig <hch@infradead.org>,
Peter Zijlstra <peterz@infradead.org>,
David Woodhouse <dwmw2@infradead.org>,
Lu Baolu <baolu.lu@linux.intel.com>,
"Hansen, Dave" <dave.hansen@intel.com>,
Randy Dunlap <rdunlap@infradead.org>,
"Raj, Ashok" <ashok.raj@intel.com>,
"Pan, Jacob jun" <jacob.jun.pan@intel.com>,
"Jiang, Dave" <dave.jiang@intel.com>,
"Mehta, Sohil" <sohil.mehta@intel.com>,
"Shankar, Ravi V" <ravi.v.shankar@intel.com>
Subject: RE: [PATCH] x86/cpufeatures: Force disable X86_FEATURE_ENQCMD and remove update_pasid()
Date: Wed, 2 Jun 2021 20:37:47 +0000 [thread overview]
Message-ID: <36866b38ec92425b879881a88acf547b@intel.com> (raw)
In-Reply-To: <87y2bv438p.ffs@nanos.tec.linutronix.de>
>> ... so on a PASID system, your trivial reproducer would theoretically
>> fire the same way and corrupt FPU state just as well.
>
> This is worse and you can't selftest it because the IPI can just hit in
> the middle of _any_ FPU state operation and corrupt state.
That sounds like we should abandon the "IPI all the other threads
to force enable the PASID for them" approach. It would just be a
nightmare of papering over cracks when the IPI was delivered at
some inconvenient moment when the recipient was in the middle
of touching xsave state.
I've told Fenghua to dig out the previous iteration of this patch where
the plan was to lazily fix the PASID_MSR in other threads in the #GP
handler.
That algorithm is very simple and easy to check. Pseudo-code:
#GP
if (usermode && current->mm->pasid && rdmsr(PASID_MSR) != valid) {
wrmsr(PASID_MSR, current->mm->pasid | PASID_VALID);
return;
}
Worst case is that some thread of a multi-threaded process that is using PASID
takes some unrelated #GP ... this code will try to fix it by enabling the PASID_MSR.
That will just #GP a second time and this test will see the MSR is already set,
so fall into the usual #GP handling code.
Seems like a better direction than trying to fix the IPI method. The virtualization
folks will like this way more because IPI in guest causes a couple of VMEXIT
so is somewhat expensive.
-Tony
next prev parent reply other threads:[~2021-06-02 20:37 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <1600187413-163670-1-git-send-email-fenghua.yu@intel.com>
2020-09-15 16:30 ` [PATCH v8 2/9] iommu/vt-d: Change flags type to unsigned int in binding mm Fenghua Yu
2020-09-18 7:42 ` [tip: x86/pasid] " tip-bot2 for Fenghua Yu
2020-09-15 16:30 ` [PATCH v8 4/9] x86/cpufeatures: Enumerate ENQCMD and ENQCMDS instructions Fenghua Yu
2020-09-18 7:42 ` [tip: x86/pasid] " tip-bot2 for Fenghua Yu
2020-09-15 16:30 ` [PATCH v8 5/9] x86/fpu/xstate: Add supervisor PASID state for ENQCMD feature Fenghua Yu
2020-09-18 7:42 ` [tip: x86/pasid] x86/fpu/xstate: Add supervisor PASID state for ENQCMD tip-bot2 for Yu-cheng Yu
2020-09-15 16:30 ` [PATCH v8 6/9] x86/msr-index: Define IA32_PASID MSR Fenghua Yu
2020-09-18 7:42 ` [tip: x86/pasid] x86/msr-index: Define an " tip-bot2 for Fenghua Yu
2020-09-15 16:30 ` [PATCH v8 9/9] x86/mmu: Allocate/free PASID Fenghua Yu
2020-09-18 7:42 ` [tip: x86/pasid] x86/mmu: Allocate/free a PASID tip-bot2 for Fenghua Yu
2021-05-29 9:17 ` [PATCH] x86/cpufeatures: Force disable X86_FEATURE_ENQCMD and remove update_pasid() Thomas Gleixner
2021-05-31 8:43 ` Borislav Petkov
2021-05-31 10:16 ` Thomas Gleixner
2021-06-02 20:37 ` Luck, Tony [this message]
2021-06-03 17:31 ` Andy Lutomirski
2021-06-09 17:32 ` Luck, Tony
2021-06-09 23:34 ` Andy Lutomirski
2021-06-25 15:46 ` Luck, Tony
2021-06-02 10:14 ` Borislav Petkov
2021-06-02 10:20 ` Thomas Gleixner
2021-06-03 11:20 ` Vinod Koul
2021-06-03 11:42 ` Borislav Petkov
2021-06-03 12:47 ` Vinod Koul
2021-06-03 14:33 ` Borislav Petkov
2021-06-02 19:49 ` [tip: x86/urgent] " tip-bot2 for Thomas Gleixner
2021-06-03 14:38 ` tip-bot2 for Thomas Gleixner
2020-09-16 8:06 ` [PATCH v8 0/9] x86: tag application address space for devices Joerg Roedel
2020-09-17 23:53 ` Fenghua Yu
[not found] ` <1600187413-163670-4-git-send-email-fenghua.yu@intel.com>
2020-09-17 7:53 ` [PATCH v8 3/9] Documentation/x86: Add documentation for SVA (Shared Virtual Addressing) Borislav Petkov
2020-09-17 14:56 ` Raj, Ashok
2020-09-17 17:18 ` Borislav Petkov
2020-09-17 17:22 ` Raj, Ashok
2020-09-17 17:30 ` Borislav Petkov
2020-09-18 16:22 ` Fenghua Yu
2020-09-18 7:42 ` [tip: x86/pasid] " tip-bot2 for Ashok Raj
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