From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from pegase2.c-s.fr (pegase2.c-s.fr [93.17.235.10]) by smtp.subspace.kernel.org (Postfix) with ESMTP id AC398296BBE; Mon, 25 Aug 2025 07:20:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=93.17.235.10 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756106458; cv=none; b=IW7PGarIr5ZlNAHqtARE+2ZORItRFsj68UaRdbVyNlkxxKckNcbNYerV1V6FL5WtuuOL/l/bNuNeFzqyDbjw+HtuUh9C+ARWRkZJFaZix+ourIUB7S+ndUyEvHlqYQY668rS+AgPl8QW0um1l7vww7+90xsXL5dsFIPfS5xp3DE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756106458; c=relaxed/simple; bh=73IQ37tskzYmvonToad8R3pHY7nT1ylYyENPfX+baes=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=hlHTRFkBAr0J+SUHmCQk6v0neCT2iksXHe0MOdYPBNw+eLs6h8J2EHRNmAD+ySpkwJ/tqWT3fShXHZMDxH3EChvElF96XtUdz1ug2sGFEKZcMzLD31P3cHHsgAzHEUnnaVNrtU2t+DEVhuQtOSkxzkchvofIkYpGhIJ4yYSYEic= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=csgroup.eu; spf=pass smtp.mailfrom=csgroup.eu; arc=none smtp.client-ip=93.17.235.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=csgroup.eu Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=csgroup.eu Received: from localhost (mailhub4.si.c-s.fr [172.26.127.67]) by localhost (Postfix) with ESMTP id 4c9M2D4bxpz9sSd; Mon, 25 Aug 2025 08:53:24 +0200 (CEST) X-Virus-Scanned: amavisd-new at c-s.fr Received: from pegase2.c-s.fr ([172.26.127.65]) by localhost (pegase2.c-s.fr [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 4916ElkUcXer; Mon, 25 Aug 2025 08:53:24 +0200 (CEST) Received: from messagerie.si.c-s.fr (messagerie.si.c-s.fr [192.168.25.192]) by pegase2.c-s.fr (Postfix) with ESMTP id 4c9M292RWPz9sSV; Mon, 25 Aug 2025 08:53:21 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by messagerie.si.c-s.fr (Postfix) with ESMTP id 3EDC08B769; Mon, 25 Aug 2025 08:53:21 +0200 (CEST) X-Virus-Scanned: amavisd-new at c-s.fr Received: from messagerie.si.c-s.fr ([127.0.0.1]) by localhost (messagerie.si.c-s.fr [127.0.0.1]) (amavisd-new, port 10023) with ESMTP id 4Ub9RjFzb6BR; Mon, 25 Aug 2025 08:53:21 +0200 (CEST) Received: from PO20335.idsi0.si.c-s.fr (unknown [10.25.207.160]) by messagerie.si.c-s.fr (Postfix) with ESMTP id 0C4968B765; Mon, 25 Aug 2025 08:53:21 +0200 (CEST) From: Christophe Leroy To: Qiang Zhao , Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Christophe Leroy , linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v3 4/6] soc: fsl: qe: Add support of IRQ in QE GPIO Date: Mon, 25 Aug 2025 08:53:19 +0200 Message-ID: <372550a2633586d2f98b077d3f520f3262ca0e2a.1756104334.git.christophe.leroy@csgroup.eu> X-Mailer: git-send-email 2.49.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756104796; l=2710; i=christophe.leroy@csgroup.eu; s=20211009; h=from:subject:message-id; bh=73IQ37tskzYmvonToad8R3pHY7nT1ylYyENPfX+baes=; b=1Mw+uBZnRMBUW5TPgXymjz8dvEQOBdUgMzXytx0Smi78Dl04GaGVcXxpPem3A54R13AakQw75 tgt//oO2kqfDJlJRyyRuRIbhnogLScEB/ixa/LUl6Zzem4yDI49rlNw X-Developer-Key: i=christophe.leroy@csgroup.eu; a=ed25519; pk=HIzTzUj91asvincQGOFx6+ZF5AoUuP9GdOtQChs7Mm0= Content-Transfer-Encoding: 8bit In the QE, a few GPIOs are IRQ capable. Similarly to commit 726bd223105c ("powerpc/8xx: Adding support of IRQ in MPC8xx GPIO"), add IRQ support to QE GPIO. Add property 'fsl,qe-gpio-irq-mask' similar to 'fsl,cpm1-gpio-irq-mask' that define which of the GPIOs have IRQs. Here is an exemple for port B of mpc8323 which has IRQs for GPIOs PB7, PB9, PB25 and PB27. qe_pio_b: gpio-controller@1418 { compatible = "fsl,mpc8323-qe-pario-bank"; reg = <0x1418 0x18>; interrupts = <4 5 6 7>; interrupt-parent = <&qepic>; gpio-controller; #gpio-cells = <2>; fsl,qe-gpio-irq-mask = <0x01400050>; }; Signed-off-by: Christophe Leroy --- drivers/soc/fsl/qe/gpio.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/soc/fsl/qe/gpio.c b/drivers/soc/fsl/qe/gpio.c index a338469cebe4..91d469403126 100644 --- a/drivers/soc/fsl/qe/gpio.c +++ b/drivers/soc/fsl/qe/gpio.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -32,6 +33,8 @@ struct qe_gpio_chip { /* saved_regs used to restore dedicated functions */ struct qe_pio_regs saved_regs; + + int irq[32]; }; static void qe_gpio_save_regs(struct qe_gpio_chip *qe_gc) @@ -135,6 +138,13 @@ static int qe_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) return 0; } +static int qe_gpio_to_irq(struct gpio_chip *gc, unsigned int gpio) +{ + struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc); + + return qe_gc->irq[gpio] ? : -ENXIO; +} + struct qe_pin { /* * The qe_gpio_chip name is unfortunate, we should change that to @@ -295,6 +305,7 @@ static int qe_gpio_probe(struct platform_device *ofdev) struct device_node *np = dev->of_node; struct qe_gpio_chip *qe_gc; struct gpio_chip *gc; + u32 mask; qe_gc = devm_kzalloc(dev, sizeof(*qe_gc), GFP_KERNEL); if (!qe_gc) @@ -302,6 +313,14 @@ static int qe_gpio_probe(struct platform_device *ofdev) spin_lock_init(&qe_gc->lock); + if (!of_property_read_u32(np, "fsl,qe-gpio-irq-mask", &mask)) { + int i, j; + + for (i = 0, j = 0; i < ARRAY_SIZE(qe_gc->irq); i++) + if (mask & (1 << (31 - i))) + qe_gc->irq[i] = irq_of_parse_and_map(np, j++); + } + gc = &qe_gc->gc; gc->base = -1; @@ -311,6 +330,7 @@ static int qe_gpio_probe(struct platform_device *ofdev) gc->get = qe_gpio_get; gc->set = qe_gpio_set; gc->set_multiple = qe_gpio_set_multiple; + gc->to_irq = qe_gpio_to_irq; gc->parent = dev; gc->owner = THIS_MODULE; -- 2.49.0