Re: [PATCH 20/21] amd64_edac: add DRAM error injection logic using sysfs

Re: [PATCH 20/21] amd64_edac: add DRAM error injection logic using sysfs

[Doug Thompson]

--- On Thu, 4/30/09, Ingo Molnar <mingo@elte.hu> wrote:

> From: Ingo Molnar <mingo@elte.hu>
> Subject: Re: [PATCH 20/21] amd64_edac: add DRAM error injection logic using sysfs
> To: "Doug Thompson" <norsk5@yahoo.com>
> Cc: "Borislav Petkov" <borislav.petkov@amd.com>, akpm@linux-foundation.org, greg@kroah.com, tglx@linutronix.de, hpa@zytor.com, dougthompson@xmission.com, linux-kernel@vger.kernel.org
> Date: Thursday, April 30, 2009, 2:34 AM
> 
> * Doug Thompson <norsk5@yahoo.com>
> wrote:
> 
> > 
> > I believe I failed to reply to ALL and replied only to
> the sender
> > 
> > doug t
> > 
> > --- On Wed, 4/29/09, Ingo Molnar <mingo@elte.hu>
> wrote:
> > 
> > > From: Ingo Molnar <mingo@elte.hu>
> > > Subject: Re: [PATCH 20/21] amd64_edac: add DRAM
> error injection logic using sysfs
> > > To: "Borislav Petkov" <borislav.petkov@amd.com>
> > > Cc: akpm@linux-foundation.org,
> greg@kroah.com, tglx@linutronix.de,
> hpa@zytor.com, dougthompson@xmission.com,
> linux-kernel@vger.kernel.org
> > > Date: Wednesday, April 29, 2009, 12:17 PM
> > > 
> > > * Borislav Petkov <borislav.petkov@amd.com>
> > > wrote:
> > > 
> > > > From: Doug Thompson <dougthompson@xmission.com>
> > > > 
> > > > Signed-off-by: Doug Thompson <dougthompson@xmission.com>
> > > > Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
> > > > ---
> > > >  drivers/edac/amd64_edac.c |  287
> > > +++++++++++++++++++++++++++++++++++++++++++++
> > > >  1 files changed, 287 insertions(+), 0
> > > deletions(-)
> > > > 
> > > > diff --git a/drivers/edac/amd64_edac.c
> > > b/drivers/edac/amd64_edac.c
> > > > index b1a7e8c..4d1076f 100644
> > > > --- a/drivers/edac/amd64_edac.c
> > > > +++ b/drivers/edac/amd64_edac.c
> > > > @@ -4621,3 +4621,290 @@ static ssize_t
> > > amd64_hole_show(struct mem_ctl_info *mci, char
> *data)
> > > >  
> > > >  #endif    /* DEBUG */
> > > >  
> > > > +#ifdef
> CONFIG_EDAC_AMD64_OPTERON_ERROR_INJECTION
> > > 
> > > this should be in a separate .c file under
> > > drivers/edac/amd64/. 
> > > 
> > > Introducing large #ifdef sections like that is
> not very
> > > clean. The 
> > > amd64_edac.c file is _way_ too large at more than
> 5000
> > > lines of 
> > > code.
> > > 
> > >     Ingo
> > 
> > If we broke this into a separate files, then there
> would be TWO 
> > (2) files: 1 for the source code of the routines and a
> 1 for the 
> > table entries which reference those routines. Is that
> then 
> > acceptable as well?
> > 
> > Same pattern applies to the DEBUG functions Info
> refers to in 
> > another thread: 2 separate files would be required as
> well.
> > 
> > 2 files for Error Injection code
> > 2 files for DEBUG controls
> > 1 files for text mapping
> > 
> > and I assume all these would be included via an
> #include statement 
> > at their appropriate locations
> 
> A Makefile might be more natural i think - that way the
> #ifdef turns 
> into a makefile rule?
> 
>     Ingo
> 

OK, yes for the separate and standalone functions themselves, but NOT for the function pointer table entries, which also share the table with the DEBUG function pointers and possibly function pointers to code that is not bracketed by #ifdefs 

The function pointer table itself is/can be composed of several entries, not just of the injection or debug kind. In this instance, that is what is there, but I would prefer to allow for future additions not tied to injection and/or debug origins nor of #ifdef bracketing

doug t

Re: [PATCH 20/21] amd64_edac: add DRAM error injection logic using sysfs

[Doug Thompson]

I believe I failed to reply to ALL and replied only to the sender

doug t

--- On Wed, 4/29/09, Ingo Molnar <mingo@elte.hu> wrote:

> From: Ingo Molnar <mingo@elte.hu>
> Subject: Re: [PATCH 20/21] amd64_edac: add DRAM error injection logic using sysfs
> To: "Borislav Petkov" <borislav.petkov@amd.com>
> Cc: akpm@linux-foundation.org, greg@kroah.com, tglx@linutronix.de, hpa@zytor.com, dougthompson@xmission.com, linux-kernel@vger.kernel.org
> Date: Wednesday, April 29, 2009, 12:17 PM
> 
> * Borislav Petkov <borislav.petkov@amd.com>
> wrote:
> 
> > From: Doug Thompson <dougthompson@xmission.com>
> > 
> > Signed-off-by: Doug Thompson <dougthompson@xmission.com>
> > Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
> > ---
> >  drivers/edac/amd64_edac.c |  287
> +++++++++++++++++++++++++++++++++++++++++++++
> >  1 files changed, 287 insertions(+), 0
> deletions(-)
> > 
> > diff --git a/drivers/edac/amd64_edac.c
> b/drivers/edac/amd64_edac.c
> > index b1a7e8c..4d1076f 100644
> > --- a/drivers/edac/amd64_edac.c
> > +++ b/drivers/edac/amd64_edac.c
> > @@ -4621,3 +4621,290 @@ static ssize_t
> amd64_hole_show(struct mem_ctl_info *mci, char *data)
> >  
> >  #endif    /* DEBUG */
> >  
> > +#ifdef CONFIG_EDAC_AMD64_OPTERON_ERROR_INJECTION
> 
> this should be in a separate .c file under
> drivers/edac/amd64/. 
> 
> Introducing large #ifdef sections like that is not very
> clean. The 
> amd64_edac.c file is _way_ too large at more than 5000
> lines of 
> code.
> 
>     Ingo

If we broke this into a separate files, then there would be TWO (2) files: 1 for the source code of the routines and a 1 for the table entries which reference those routines. Is that then acceptable as well?

Same pattern applies to the DEBUG functions Info refers to in another thread:  2 separate files would be required as well.

2 files for Error Injection code
2 files for DEBUG controls
1 files for text mapping

and I assume all these would be included via an #include statement at their appropriate locations

thx

doug t

Re: [PATCH 20/21] amd64_edac: add DRAM error injection logic using sysfs

[Ingo Molnar]

* Doug Thompson <norsk5@yahoo.com> wrote:

> 
> I believe I failed to reply to ALL and replied only to the sender
> 
> doug t
> 
> --- On Wed, 4/29/09, Ingo Molnar <mingo@elte.hu> wrote:
> 
> > From: Ingo Molnar <mingo@elte.hu>
> > Subject: Re: [PATCH 20/21] amd64_edac: add DRAM error injection logic using sysfs
> > To: "Borislav Petkov" <borislav.petkov@amd.com>
> > Cc: akpm@linux-foundation.org, greg@kroah.com, tglx@linutronix.de, hpa@zytor.com, dougthompson@xmission.com, linux-kernel@vger.kernel.org
> > Date: Wednesday, April 29, 2009, 12:17 PM
> > 
> > * Borislav Petkov <borislav.petkov@amd.com>
> > wrote:
> > 
> > > From: Doug Thompson <dougthompson@xmission.com>
> > > 
> > > Signed-off-by: Doug Thompson <dougthompson@xmission.com>
> > > Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
> > > ---
> > >  drivers/edac/amd64_edac.c |  287
> > +++++++++++++++++++++++++++++++++++++++++++++
> > >  1 files changed, 287 insertions(+), 0
> > deletions(-)
> > > 
> > > diff --git a/drivers/edac/amd64_edac.c
> > b/drivers/edac/amd64_edac.c
> > > index b1a7e8c..4d1076f 100644
> > > --- a/drivers/edac/amd64_edac.c
> > > +++ b/drivers/edac/amd64_edac.c
> > > @@ -4621,3 +4621,290 @@ static ssize_t
> > amd64_hole_show(struct mem_ctl_info *mci, char *data)
> > >  
> > >  #endif    /* DEBUG */
> > >  
> > > +#ifdef CONFIG_EDAC_AMD64_OPTERON_ERROR_INJECTION
> > 
> > this should be in a separate .c file under
> > drivers/edac/amd64/. 
> > 
> > Introducing large #ifdef sections like that is not very
> > clean. The 
> > amd64_edac.c file is _way_ too large at more than 5000
> > lines of 
> > code.
> > 
> >     Ingo
> 
> If we broke this into a separate files, then there would be TWO 
> (2) files: 1 for the source code of the routines and a 1 for the 
> table entries which reference those routines. Is that then 
> acceptable as well?
> 
> Same pattern applies to the DEBUG functions Info refers to in 
> another thread: 2 separate files would be required as well.
> 
> 2 files for Error Injection code
> 2 files for DEBUG controls
> 1 files for text mapping
> 
> and I assume all these would be included via an #include statement 
> at their appropriate locations

A Makefile might be more natural i think - that way the #ifdef turns 
into a makefile rule?

	Ingo

[RFC PATCH 00/21 v2] amd64_edac: EDAC module for AMD64

[Borislav Petkov]

Hi,

thanks to all reviewers of the previous submission, here is the second
version of this series.

Highlights are the addition of two helpers to read/write MSRs on several
CPUs, denoted by a cpumask and using an array of MSR values per-CPU, as
Peter suggested. Since IMHO they look generic enough I've added them to
arch/x86/lib/msr-on-cpu.c (now renamed to msr.c).

Moreover, I've addressed all the issues raised from the previous series.
Please let me know should there be anything else remaining.

Thanks,
Boris.

 arch/x86/include/asm/msr.h |   11 +
 arch/x86/lib/Makefile      |    2 +-
 arch/x86/lib/msr-on-cpu.c  |   97 -
 arch/x86/lib/msr.c         |  151 ++
 drivers/edac/Kconfig       |   26 +
 drivers/edac/Makefile      |    1 +
 drivers/edac/amd64_edac.c  | 5385 ++++++++++++++++++++++++++++++++++++++++++++
 7 files changed, 5575 insertions(+), 98 deletions(-)

[PATCH 20/21] amd64_edac: add DRAM error injection logic using sysfs

[Borislav Petkov]

From: Doug Thompson <dougthompson@xmission.com>

Signed-off-by: Doug Thompson <dougthompson@xmission.com>
Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
---
 drivers/edac/amd64_edac.c |  287 +++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 287 insertions(+), 0 deletions(-)

diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index b1a7e8c..4d1076f 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -4621,3 +4621,290 @@ static ssize_t amd64_hole_show(struct mem_ctl_info *mci, char *data)
 
 #endif	/* DEBUG */
 
+#ifdef CONFIG_EDAC_AMD64_OPTERON_ERROR_INJECTION
+/*
+ * amd64_inject_section_store
+ *
+ *	accept and store error injection section value
+ *	range: 0..3
+ *		value refers to one of 4 16-byte sections
+ *		within a 64-byte cacheline
+ */
+static ssize_t amd64_inject_section_store(struct mem_ctl_info *mci,
+					const char *data, size_t count)
+{
+	struct amd64_pvt *pvt = mci->pvt_info;
+	unsigned long value;
+	int rc;
+
+	rc = strict_strtoul(data, 10, &value);
+	if (rc != -EINVAL) {
+
+		/* save the 16-byte cache section */
+		pvt->injection.section = (u32) value;
+
+		return count;
+	}
+	return 0;
+}
+
+/*
+ * amd64_inject_word_store
+ *
+ *	accept and store error injection word value
+ *	range: 0..8
+ *		value refers to one of 9 16-bit word of the 16-byte section
+ *		128-bit + ECC bits
+ */
+static ssize_t amd64_inject_word_store(struct mem_ctl_info *mci,
+					const char *data, size_t count)
+{
+	struct amd64_pvt *pvt = mci->pvt_info;
+	unsigned long value;
+	int rc;
+
+	rc = strict_strtoul(data, 10, &value);
+	if (rc != -EINVAL) {
+
+		/* save the 16-bit word */
+		value = (value <= 8) ? value : 0;
+		pvt->injection.word = (u32) value;
+
+		return count;
+	}
+	return 0;
+}
+
+/*
+ * amd64_inject_bit_store
+ *
+ *	accept and store error injection hexidecimal bit value
+ *	16-bits of a bit-vector marking which bits to error-out on
+ */
+static ssize_t amd64_inject_bit_store(struct mem_ctl_info *mci,
+					const char *data, size_t count)
+{
+	struct amd64_pvt *pvt = mci->pvt_info;
+	unsigned long value;
+	int rc;
+
+	rc = strict_strtoul(data, 16, &value);
+	if (rc != -EINVAL) {
+
+		/* save the bit within the 16-bit word */
+		pvt->injection.bit_map = (u32) value & 0xFFFF;
+
+		return count;
+	}
+	return 0;
+}
+
+/*
+ * amd64_inject_read_store
+ *
+ *	READ action. When called, assemble staged values in the pvt
+ *	area and format into fields needed by the Injection hardware
+ *	Output to hardware and issue a READ operation
+ */
+static ssize_t amd64_inject_read_store(struct mem_ctl_info *mci,
+					const char *data, size_t count)
+{
+	struct amd64_pvt *pvt = mci->pvt_info;
+	unsigned long value;
+	u32 section, word_bits;
+	int rc;
+
+	rc = strict_strtoul(data, 10, &value);
+	if (rc != -EINVAL) {
+
+		/* Form value to choose 16-byte section of cacheline */
+		section = F10_NB_ARRAY_DRAM_ECC |
+				SET_NB_ARRAY_ADDRESS(pvt->injection.section);
+		pci_write_config_dword(pvt->misc_f3_ctl,
+					F10_NB_ARRAY_ADDR, section);
+
+		word_bits = SET_NB_DRAM_INJECTION_READ(pvt->injection.word,
+						pvt->injection.bit_map);
+
+		/* Issue 'word' and 'bit' along with the READ request now */
+		pci_write_config_dword(pvt->misc_f3_ctl,
+					F10_NB_ARRAY_DATA, word_bits);
+
+		debugf0("%s() section=0x%x word_bits=0x%x\n", __func__,
+			section, word_bits);
+
+		return count;
+	}
+	return 0;
+}
+
+/*
+ * amd64_inject_write_store
+ *
+ *	WRITE action. When called, assemble staged values in the pvt
+ *	area and format into fields needed by the Injection hardware
+ *	Output to hardware and issue a WRITE operation
+ */
+static ssize_t amd64_inject_write_store(struct mem_ctl_info *mci,
+					const char *data, size_t count)
+{
+	struct amd64_pvt *pvt = mci->pvt_info;
+	unsigned long value;
+	u32 section, word_bits;
+	int rc;
+
+	rc = strict_strtoul(data, 10, &value);
+	if (rc != -EINVAL) {
+
+		/* Form value to choose 16-byte section of cacheline */
+		section = F10_NB_ARRAY_DRAM_ECC |
+				SET_NB_ARRAY_ADDRESS(pvt->injection.section);
+		pci_write_config_dword(pvt->misc_f3_ctl,
+					F10_NB_ARRAY_ADDR, section);
+
+		word_bits = SET_NB_DRAM_INJECTION_WRITE(pvt->injection.word,
+						pvt->injection.bit_map);
+
+		/* Issue 'word' and 'bit' along with the READ request now */
+		pci_write_config_dword(pvt->misc_f3_ctl,
+					F10_NB_ARRAY_DATA, word_bits);
+
+		debugf0("%s() section=0x%x word_bits=0x%x\n", __func__,
+			section, word_bits);
+
+		return count;
+	}
+	return 0;
+}
+#endif
+
+/*
+ * Per MC instance Attribute/Control data control structure
+ *	Can add for debug or for normal use
+ */
+static struct mcidev_sysfs_attribute amd64_mc_sysfs_ctls_attrs[] = {
+
+#ifdef CONFIG_EDAC_AMD64_OPTERON_ERROR_INJECTION
+	/* Error injection methods */
+	{
+		.attr = {
+			.name = "z_inject_section",
+			.mode = (S_IRUGO | S_IWUSR)
+		},
+		.show = NULL,
+		.store = amd64_inject_section_store,
+	},
+	{
+		.attr = {
+			.name = "z_inject_word",
+			.mode = (S_IRUGO | S_IWUSR)
+		},
+		.show = NULL,
+		.store = amd64_inject_word_store,
+	},
+	{
+		.attr = {
+			.name = "z_inject_bit_map",
+			.mode = (S_IRUGO | S_IWUSR)
+		},
+		.show = NULL,
+		.store = amd64_inject_bit_store,
+	},
+	{
+		.attr = {
+			.name = "z_inject_write",
+			.mode = (S_IRUGO | S_IWUSR)
+		},
+		.show = NULL,
+		.store = amd64_inject_write_store,
+	},
+	{
+		.attr = {
+			.name = "z_inject_read",
+			.mode = (S_IRUGO | S_IWUSR)
+		},
+		.show = NULL,
+		.store = amd64_inject_read_store,
+	},
+#endif	/* CONFIG_EDAC_AMD64_OPTERON_ERROR_INJECTION */
+
+#ifdef	CONFIG_EDAC_DEBUG
+	/* RAW register accessors */
+	{
+		.attr = {
+			.name = "zctl_nbea",
+			.mode = (S_IRUGO | S_IWUSR)
+		},
+		.show = amd64_nbea_show,
+		.store = amd64_nbea_store,
+	},
+	{
+		.attr = {
+			.name = "zctl_nbsl",
+			.mode = (S_IRUGO | S_IWUSR)
+		},
+		.show = amd64_nbsl_show,
+		.store = amd64_nbsl_store,
+	},
+	{
+		.attr = {
+			.name = "zctl_nbsh",
+			.mode = (S_IRUGO | S_IWUSR)
+		},
+		.show = amd64_nbsh_show,
+		.store = amd64_nbsh_store,
+	},
+	{
+		.attr = {
+			.name = "zctl_nbcfg",
+			.mode = (S_IRUGO | S_IWUSR)
+		},
+		.show = amd64_nbcfg_show,
+		.store = amd64_nbcfg_store,
+	},
+	{
+		.attr = {
+			.name = "zhw_dhar",
+			.mode = (S_IRUGO)
+		},
+		.show = amd64_dhar_show,
+		.store = NULL,
+	},
+	{
+		.attr = {
+			.name = "zhw_dbam",
+			.mode = (S_IRUGO)
+		},
+		.show = amd64_dbam_show,
+		.store = NULL,
+	},
+	{
+		.attr = {
+			.name = "zhw_topmem",
+			.mode = (S_IRUGO)
+		},
+		.show = amd64_topmem_show,
+		.store = NULL,
+	},
+	{
+		.attr = {
+			.name = "zhw_topmem2",
+			.mode = (S_IRUGO)
+		},
+		.show = amd64_topmem2_show,
+		.store = NULL,
+	},
+	{
+		.attr = {
+			.name = "zhw_hole",
+			.mode = (S_IRUGO)
+		},
+		.show = amd64_hole_show,
+		.store = NULL,
+	},
+#endif
+	{
+		.attr = { .name = NULL}
+	}
+};
+
-- 
1.6.2.4

Re: [PATCH 20/21] amd64_edac: add DRAM error injection logic using sysfs

[Ingo Molnar]

* Borislav Petkov <borislav.petkov@amd.com> wrote:

> From: Doug Thompson <dougthompson@xmission.com>
> 
> Signed-off-by: Doug Thompson <dougthompson@xmission.com>
> Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
> ---
>  drivers/edac/amd64_edac.c |  287 +++++++++++++++++++++++++++++++++++++++++++++
>  1 files changed, 287 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
> index b1a7e8c..4d1076f 100644
> --- a/drivers/edac/amd64_edac.c
> +++ b/drivers/edac/amd64_edac.c
> @@ -4621,3 +4621,290 @@ static ssize_t amd64_hole_show(struct mem_ctl_info *mci, char *data)
>  
>  #endif	/* DEBUG */
>  
> +#ifdef CONFIG_EDAC_AMD64_OPTERON_ERROR_INJECTION

this should be in a separate .c file under drivers/edac/amd64/. 

Introducing large #ifdef sections like that is not very clean. The 
amd64_edac.c file is _way_ too large at more than 5000 lines of 
code.

	Ingo

Re: [PATCH 20/21] amd64_edac: add DRAM error injection logic using sysfs

[Mauro Carvalho Chehab]

Borislav Petkov escreveu:
> From: Doug Thompson <dougthompson@xmission.com>
>
> Signed-off-by: Doug Thompson <dougthompson@xmission.com>
> Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
> ---
>  drivers/edac/amd64_edac.c |  287 +++++++++++++++++++++++++++++++++++++++++++++
>  1 files changed, 287 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
> index b1a7e8c..4d1076f 100644
> --- a/drivers/edac/amd64_edac.c
> +++ b/drivers/edac/amd64_edac.c
> @@ -4621,3 +4621,290 @@ static ssize_t amd64_hole_show(struct mem_ctl_info *mci, char *data)
>  
>  #endif	/* DEBUG */
>  
> +#ifdef CONFIG_EDAC_AMD64_OPTERON_ERROR_INJECTION
> +/*
> + * amd64_inject_section_store
> + *
> + *	accept and store error injection section value
> + *	range: 0..3
> + *		value refers to one of 4 16-byte sections
> + *		within a 64-byte cacheline
> + */
> +static ssize_t amd64_inject_section_store(struct mem_ctl_info *mci,
> +					const char *data, size_t count)
> +{
> +	struct amd64_pvt *pvt = mci->pvt_info;
> +	unsigned long value;
> +	int rc;
> +
> +	rc = strict_strtoul(data, 10, &value);
> +	if (rc != -EINVAL) {
> +
> +		/* save the 16-byte cache section */
> +		pvt->injection.section = (u32) value;
> +
> +		return count;
> +	}
> +	return 0;
> +}
> +
> +/*
> + * amd64_inject_word_store
> + *
> + *	accept and store error injection word value
> + *	range: 0..8
> + *		value refers to one of 9 16-bit word of the 16-byte section
> + *		128-bit + ECC bits
> + */
> +static ssize_t amd64_inject_word_store(struct mem_ctl_info *mci,
> +					const char *data, size_t count)
> +{
> +	struct amd64_pvt *pvt = mci->pvt_info;
> +	unsigned long value;
> +	int rc;
> +
> +	rc = strict_strtoul(data, 10, &value);
> +	if (rc != -EINVAL) {
> +
> +		/* save the 16-bit word */
> +		value = (value <= 8) ? value : 0;
> +		pvt->injection.word = (u32) value;
> +
> +		return count;
> +	}
> +	return 0;
> +}
> +
> +/*
> + * amd64_inject_bit_store
> + *
> + *	accept and store error injection hexidecimal bit value
> + *	16-bits of a bit-vector marking which bits to error-out on
> + */
> +static ssize_t amd64_inject_bit_store(struct mem_ctl_info *mci,
> +					const char *data, size_t count)
> +{
> +	struct amd64_pvt *pvt = mci->pvt_info;
> +	unsigned long value;
> +	int rc;
> +
> +	rc = strict_strtoul(data, 16, &value);
> +	if (rc != -EINVAL) {
> +
> +		/* save the bit within the 16-bit word */
> +		pvt->injection.bit_map = (u32) value & 0xFFFF;
> +
> +		return count;
> +	}
> +	return 0;
> +}
> +
> +/*
> + * amd64_inject_read_store
> + *
> + *	READ action. When called, assemble staged values in the pvt
> + *	area and format into fields needed by the Injection hardware
> + *	Output to hardware and issue a READ operation
> + */
> +static ssize_t amd64_inject_read_store(struct mem_ctl_info *mci,
> +					const char *data, size_t count)
> +{
> +	struct amd64_pvt *pvt = mci->pvt_info;
> +	unsigned long value;
> +	u32 section, word_bits;
> +	int rc;
> +
> +	rc = strict_strtoul(data, 10, &value);
> +	if (rc != -EINVAL) {
> +
> +		/* Form value to choose 16-byte section of cacheline */
> +		section = F10_NB_ARRAY_DRAM_ECC |
> +				SET_NB_ARRAY_ADDRESS(pvt->injection.section);
> +		pci_write_config_dword(pvt->misc_f3_ctl,
> +					F10_NB_ARRAY_ADDR, section);
> +
> +		word_bits = SET_NB_DRAM_INJECTION_READ(pvt->injection.word,
> +						pvt->injection.bit_map);
> +
> +		/* Issue 'word' and 'bit' along with the READ request now */
> +		pci_write_config_dword(pvt->misc_f3_ctl,
> +					F10_NB_ARRAY_DATA, word_bits);
> +
> +		debugf0("%s() section=0x%x word_bits=0x%x\n", __func__,
> +			section, word_bits);
> +
> +		return count;
> +	}
> +	return 0;
> +}
> +
> +/*
> + * amd64_inject_write_store
> + *
> + *	WRITE action. When called, assemble staged values in the pvt
> + *	area and format into fields needed by the Injection hardware
> + *	Output to hardware and issue a WRITE operation
> + */
> +static ssize_t amd64_inject_write_store(struct mem_ctl_info *mci,
> +					const char *data, size_t count)
> +{
> +	struct amd64_pvt *pvt = mci->pvt_info;
> +	unsigned long value;
> +	u32 section, word_bits;
> +	int rc;
> +
> +	rc = strict_strtoul(data, 10, &value);
> +	if (rc != -EINVAL) {
> +
> +		/* Form value to choose 16-byte section of cacheline */
> +		section = F10_NB_ARRAY_DRAM_ECC |
> +				SET_NB_ARRAY_ADDRESS(pvt->injection.section);
> +		pci_write_config_dword(pvt->misc_f3_ctl,
> +					F10_NB_ARRAY_ADDR, section);
> +
> +		word_bits = SET_NB_DRAM_INJECTION_WRITE(pvt->injection.word,
> +						pvt->injection.bit_map);
> +
> +		/* Issue 'word' and 'bit' along with the READ request now */
> +		pci_write_config_dword(pvt->misc_f3_ctl,
> +					F10_NB_ARRAY_DATA, word_bits);
> +
> +		debugf0("%s() section=0x%x word_bits=0x%x\n", __func__,
> +			section, word_bits);
> +
> +		return count;
> +	}
> +	return 0;
> +}
> +#endif
> +
> +/*
> + * Per MC instance Attribute/Control data control structure
> + *	Can add for debug or for normal use
> + */
> +static struct mcidev_sysfs_attribute amd64_mc_sysfs_ctls_attrs[] = {
> +
> +#ifdef CONFIG_EDAC_AMD64_OPTERON_ERROR_INJECTION
> +	/* Error injection methods */
> +	{
> +		.attr = {
> +			.name = "z_inject_section",
> +			.mode = (S_IRUGO | S_IWUSR)
> +		},
> +		.show = NULL,
> +		.store = amd64_inject_section_store,
> +	},
> +	{
> +		.attr = {
> +			.name = "z_inject_word",
> +			.mode = (S_IRUGO | S_IWUSR)
> +		},
> +		.show = NULL,
> +		.store = amd64_inject_word_store,
> +	},
> +	{
> +		.attr = {
> +			.name = "z_inject_bit_map",
> +			.mode = (S_IRUGO | S_IWUSR)
> +		},
> +		.show = NULL,
> +		.store = amd64_inject_bit_store,
> +	},
> +	{
> +		.attr = {
> +			.name = "z_inject_write",
> +			.mode = (S_IRUGO | S_IWUSR)
> +		},
> +		.show = NULL,
> +		.store = amd64_inject_write_store,
> +	},
> +	{
> +		.attr = {
> +			.name = "z_inject_read",
> +			.mode = (S_IRUGO | S_IWUSR)
> +		},
> +		.show = NULL,
> +		.store = amd64_inject_read_store,
> +	},
> +#endif	/* CONFIG_EDAC_AMD64_OPTERON_ERROR_INJECTION */
> +
> +#ifdef	CONFIG_EDAC_DEBUG
> +	/* RAW register accessors */
> +	{
> +		.attr = {
> +			.name = "zctl_nbea",
> +			.mode = (S_IRUGO | S_IWUSR)
> +		},
> +		.show = amd64_nbea_show,
> +		.store = amd64_nbea_store,
> +	},
> +	{
> +		.attr = {
> +			.name = "zctl_nbsl",
> +			.mode = (S_IRUGO | S_IWUSR)
> +		},
> +		.show = amd64_nbsl_show,
> +		.store = amd64_nbsl_store,
> +	},
> +	{
> +		.attr = {
> +			.name = "zctl_nbsh",
> +			.mode = (S_IRUGO | S_IWUSR)
> +		},
> +		.show = amd64_nbsh_show,
> +		.store = amd64_nbsh_store,
> +	},
> +	{
> +		.attr = {
> +			.name = "zctl_nbcfg",
> +			.mode = (S_IRUGO | S_IWUSR)
> +		},
> +		.show = amd64_nbcfg_show,
> +		.store = amd64_nbcfg_store,
> +	},
> +	{
> +		.attr = {
> +			.name = "zhw_dhar",
> +			.mode = (S_IRUGO)
> +		},
> +		.show = amd64_dhar_show,
> +		.store = NULL,
> +	},
> +	{
> +		.attr = {
> +			.name = "zhw_dbam",
> +			.mode = (S_IRUGO)
> +		},
> +		.show = amd64_dbam_show,
> +		.store = NULL,
> +	},
> +	{
> +		.attr = {
> +			.name = "zhw_topmem",
> +			.mode = (S_IRUGO)
> +		},
> +		.show = amd64_topmem_show,
> +		.store = NULL,
> +	},
> +	{
> +		.attr = {
> +			.name = "zhw_topmem2",
> +			.mode = (S_IRUGO)
> +		},
> +		.show = amd64_topmem2_show,
> +		.store = NULL,
> +	},
> +	{
> +		.attr = {
> +			.name = "zhw_hole",
> +			.mode = (S_IRUGO)
> +		},
> +		.show = amd64_hole_show,
> +		.store = NULL,
> +	},
> +#endif
> +	{
> +		.attr = { .name = NULL}
> +	}
> +};
> +
>   
The code looks fine. I agree with Ingo: It is better to move such large 
#ifdefs present on patches 19 and 20 into a separate c file.

Cheers,
Mauro.

[RFC PATCH 00/21] amd64_edac: EDAC module for AMD64

[Borislav Petkov]

Hi Andrew,
hi Greg,

I think you've already heard about this driver, so here is a first
upstream submission request. It is quite sizable but partly the reason
for it is that it handles ECC detection and reporting for all AMD
K8, F10h and F11h families. It also implements DRAM error injection
functionality, failing DIMM module detection and some other fun stuff
found on F10h and later CPUs.

We've been doing testing/bugfixing/scrubbing here for some time, have
converted it to using kernel facilities and basically removed some slack
from it like glue code due to it being maintained out-of-tree. Please
take a look and let us know of any objections/comments you might have so
that we could tackle them on time.

Thanks in advance.

 drivers/edac/Kconfig      |   26 +
 drivers/edac/Makefile     |    1 +
 drivers/edac/amd64_edac.c | 5249 +++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 5276 insertions(+), 0 deletions(-)

[PATCH 20/21] amd64_edac: add DRAM error injection logic using sysfs

[Borislav Petkov]

From: Doug Thompson <dougthompson@xmission.com>

Signed-off-by: Doug Thompson <dougthompson@xmission.com>
Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
---
 drivers/edac/amd64_edac.c |  130 +++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 130 insertions(+), 0 deletions(-)

diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index 3c04fd6..1f62346 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -4654,3 +4654,133 @@ static ssize_t amd64_hole_show(struct mem_ctl_info *mci, char *data)
 
 #endif	/* DEBUG */
 
+/*
+ * Per MC instance Attribute/Control data control structure
+ *	Can add for debug or for normal use
+ */
+static struct mcidev_sysfs_attribute amd64_mc_sysfs_ctls_attrs[] = {
+
+#ifdef CONFIG_EDAC_AMD64_OPTERON_ERROR_INJECTION
+	/* Error injection methods */
+	{
+		.attr = {
+			.name = "z_inject_section",
+			.mode = (S_IRUGO | S_IWUSR)
+		},
+		.show = NULL,
+		.store = amd64_inject_section_store,
+	},
+	{
+		.attr = {
+			.name = "z_inject_word",
+			.mode = (S_IRUGO | S_IWUSR)
+		},
+		.show = NULL,
+		.store = amd64_inject_word_store,
+	},
+	{
+		.attr = {
+			.name = "z_inject_bit_map",
+			.mode = (S_IRUGO | S_IWUSR)
+		},
+		.show = NULL,
+		.store = amd64_inject_bit_store,
+	},
+	{
+		.attr = {
+			.name = "z_inject_write",
+			.mode = (S_IRUGO | S_IWUSR)
+		},
+		.show = NULL,
+		.store = amd64_inject_write_store,
+	},
+	{
+		.attr = {
+			.name = "z_inject_read",
+			.mode = (S_IRUGO | S_IWUSR)
+		},
+		.show = NULL,
+		.store = amd64_inject_read_store,
+	},
+#endif	/* CONFIG_EDAC_AMD64_OPTERON_ERROR_INJECTION */
+
+#ifdef	CONFIG_EDAC_DEBUG
+	/* RAW register accessors */
+	{
+		.attr = {
+			.name = "zctl_nbea",
+			.mode = (S_IRUGO | S_IWUSR)
+		},
+		.show = amd64_nbea_show,
+		.store = amd64_nbea_store,
+	},
+	{
+		.attr = {
+			.name = "zctl_nbsl",
+			.mode = (S_IRUGO | S_IWUSR)
+		},
+		.show = amd64_nbsl_show,
+		.store = amd64_nbsl_store,
+	},
+	{
+		.attr = {
+			.name = "zctl_nbsh",
+			.mode = (S_IRUGO | S_IWUSR)
+		},
+		.show = amd64_nbsh_show,
+		.store = amd64_nbsh_store,
+	},
+	{
+		.attr = {
+			.name = "zctl_nbcfg",
+			.mode = (S_IRUGO | S_IWUSR)
+		},
+		.show = amd64_nbcfg_show,
+		.store = amd64_nbcfg_store,
+	},
+	{
+		.attr = {
+			.name = "zhw_dhar",
+			.mode = (S_IRUGO)
+		},
+		.show = amd64_dhar_show,
+		.store = NULL,
+	},
+	{
+		.attr = {
+			.name = "zhw_dbam",
+			.mode = (S_IRUGO)
+		},
+		.show = amd64_dbam_show,
+		.store = NULL,
+	},
+	{
+		.attr = {
+			.name = "zhw_topmem",
+			.mode = (S_IRUGO)
+		},
+		.show = amd64_topmem_show,
+		.store = NULL,
+	},
+	{
+		.attr = {
+			.name = "zhw_topmem2",
+			.mode = (S_IRUGO)
+		},
+		.show = amd64_topmem2_show,
+		.store = NULL,
+	},
+	{
+		.attr = {
+			.name = "zhw_hole",
+			.mode = (S_IRUGO)
+		},
+		.show = amd64_hole_show,
+		.store = NULL,
+	},
+#endif
+	{
+		.attr = { .name = NULL}
+	}
+};
+
-- 
1.6.2.4