Re: [PATCH 06/12] riscv: dts: allwinner: Add the D1 SoC base devicetree

Jessica Clarke
2022-08-22T15:29:27Z

On 22 Aug 2022, at 14:56, conor.dooley@microchip.com wrote:
>
> On 22/08/2022 13:31, Geert Uytterhoeven wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>
>
>
>>> Do you think this is worth doing? Or are you just providing an
>>> example of what could be done?
>>
>> Just some brainstorming...
>>
>>> Where would you envisage putting these macros? I forget the order
>>> of the CPP operations that are done, can they be put in the dts?
>>
>> The SOC_PERIPHERAL_IRQ() macro should be defined in the
>> ARM-based SoC.dtsi file and the RISC-V-based SoC.dtsi file.
>
> Right, one level up but ~the same result.
>
>
>>>> Nice! But it's gonna be a very large interrupt-map.
>>>
>>> I quite like the idea of not duplicating files across the archs
>>> if it can be helped, but not at the expense of making them hard to
>>> understand & I feel like unfortunately the large interrupt map is
>>> in that territory.
>>
>> I feel the same.
>> Even listing both interrupt numbers in SOC_PERIPHERAL_IRQ(na, nr)
>> is a risk for making mistakes.
>>
>> So personally, I'm in favor of teaching dtc arithmetic, so we can
>> handle the offset in SOC_PERIPHERAL_IRQ().
>
> Yup, in the same boat here. mayb I'll get bored enough to bite..

Note that GPL’ed dtc isn’t the only implementation. FreeBSD uses a
BSD-licensed implementation[1] and so adding new features like this to
GPL dtc that actually get used would require us to reimplement it too.
I don’t know how much effort it would be but please keep this in mind.

Jess

[1] https://github.com/davidchisnall/dtc