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From: Arnd Bergmann <arnd@arndb.de>
To: linux-arm-kernel@lists.infradead.org
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>,
        Thomas Gleixner <tglx@linutronix.de>,
        Jason Cooper <jason@lakedaemon.net>,
        Marc Zyngier <marc.zyngier@arm.com>, linux-kernel@vger.kernel.org,
        Lior Amsalem <alior@marvell.com>, Andrew Lunn <andrew@lunn.ch>,
        Nadav Haklai <nadavh@marvell.com>,
        Gregory Clement <gregory.clement@free-electrons.com>,
        Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Subject: Re: [PATCH v2] irqchip: irq-mvebu-odmi: new driver for platform MSI on Marvell 7K/8K
Date: Thu, 18 Feb 2016 17:08:05 +0100
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On Thursday 18 February 2016 16:58:54 Thomas Petazzoni wrote:
> +- marvell,spi-base     : List of GIC base SPI interrupts, one for each
> +                         ODMI frame. Those SPI interrupts are 0-based,
> +                         i.e marvell,spi-base = <128> will use SPI #96.
> +                         See Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt
> +                         for details about the GIC Device Tree binding.
> 

Why are these not just in an 'interrupts' property as we do for other
nested irqchips?

	Arnd