From: "Koralahalli Channabasappa, Smita" <skoralah@amd.com>
To: Borislav Petkov <bp@alien8.de>,
"Luck, Tony" <tony.luck@intel.com>,
Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com>
Cc: x86@kernel.org, linux-edac@vger.kernel.org,
linux-kernel@vger.kernel.org, "H . Peter Anvin" <hpa@zytor.com>,
Dave Hansen <dave.hansen@linux.intel.com>,
Yazen Ghannam <yazen.ghannam@amd.com>
Subject: Re: [RFC PATCH 1/2] x86/mce: Handle AMD threshold interrupt storms
Date: Wed, 23 Feb 2022 16:22:13 -0600 [thread overview]
Message-ID: <3979d97f-464c-e1f4-d648-526b3121dd63@amd.com> (raw)
In-Reply-To: <Yg992OrUbfmtRizs@zn.tnic>
On 2/18/22 5:07 AM, Borislav Petkov wrote:
> On Thu, Feb 17, 2022 at 09:28:09AM -0800, Luck, Tony wrote:
>> I've been sitting on some partially done patches to re-work
>> storm handling for Intel ... which rips out all the existing
>> storm bits and replaces with something all new. I'll post the
>> 2-part series as replies to this.
> Which begs the obvious question: how much of that code can be shared
> between the two?
>
It looks to me most of the code can be shared except in few places
where AMD and Intel use different registers to set error thresholds.
And the fact that AMD's threshold interrupts just handles corrected
errors unlike CMCI.
I'm thinking of coming up with a shared code between both by keeping
the Intel's new storm handling code as base and incorporating AMD
changes on them and send for review.
Let me know if thats okay?
Thanks,
Smita
next prev parent reply other threads:[~2022-02-23 22:22 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-17 14:16 [RFC PATCH 0/2] Handle AMD threshold interrupt storms Smita Koralahalli
2022-02-17 14:16 ` [RFC PATCH 1/2] x86/mce: " Smita Koralahalli
2022-02-17 17:28 ` Luck, Tony
2022-02-17 17:35 ` [PATCH 1/2] x86/mce: Remove old CMCI storm mitigation code Luck, Tony
2022-02-24 15:14 ` Borislav Petkov
2022-02-17 17:36 ` [PATCH 2/2] x86/mce: Add per-bank CMCI storm mitigation Luck, Tony
2022-02-23 22:11 ` Koralahalli Channabasappa, Smita
2022-03-07 13:31 ` Borislav Petkov
2022-03-07 20:04 ` Luck, Tony
2022-02-18 11:07 ` [RFC PATCH 1/2] x86/mce: Handle AMD threshold interrupt storms Borislav Petkov
2022-02-23 22:22 ` Koralahalli Channabasappa, Smita [this message]
2022-02-23 23:03 ` Luck, Tony
2022-03-15 18:15 ` [PATCH v2 0/2] New CMCI storm mitigation for Intel CPUs Tony Luck
2022-03-15 18:15 ` [PATCH v2 1/2] x86/mce: Remove old CMCI storm mitigation code Tony Luck
2022-03-15 18:15 ` [PATCH v2 2/2] x86/mce: Add per-bank CMCI storm mitigation Tony Luck
2022-03-15 18:34 ` [PATCH v2 0/2] New CMCI storm mitigation for Intel CPUs Borislav Petkov
2022-03-15 21:46 ` Koralahalli Channabasappa, Smita
2022-02-17 14:16 ` [RFC PATCH 2/2] x86/mce: Simplify code in log_and_reset_block() Smita Koralahalli
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