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charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Info: AW1haW4tMjYwNjE1MDA1NiBTYWx0ZWRfX4UTziOKcyypk iEmvNmRhI6UEJqsQqxkyKwhyKWW/saZmA8OkNaxPbzwu+vPAfymeFEbJ9xPALPhdthFks3bVtJd HrltNk6fEPdLbuFxlbLaSTVN0oV+cx0= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjE1MDA1NiBTYWx0ZWRfXxW3Dp+SlZXh6 fck6s2NuCMQa5C8HoqxjJCpBTBnVliIYgKw1XPuUAKkT8nSk3z9Jw+RZLpppQVopzUghp1FU9jD D2fKFKufCQoDSzEWvkk4nUQAOV6IqBl+xN/eD7J6GRobyZY3b7pe+bFYcYhVy1sIOGYoo8reN3V aJ1Hn0OUErlgZPcyPa50nSeF2dT8Rrm7r2AbUpWeL1gjkM/twlkvIWQK+ffLO39N+8thCCAZk2T 4zDiBNiOylprF0YElvUTS72mxMEekoDju8DL9BtY5Tb+qubCYDbz5TvshNiredRYXfm9urv7HS1 D8vKRkDRhxPuGiN3cdOQi1ha9I9NSED0dmmCjkyefkMliLlX8Obes7H1eTSom/Yiuo1RF/bRdAz xr6XWKBBMwRfYsFbSS+As/LyfMEsquRSXhtHywYlI2MKv6k//nPZr0LLcdPmEQvg4+y9PIiikWh SGRgcWsJsHyfH0rQRZA== X-Authority-Analysis: v=2.4 cv=NrThtcdJ c=1 sm=1 tr=0 ts=6a2f8f3b cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=NEAV23lmAAAA:8 a=F36j7lWHSACE9dnm3LoA:9 a=QEXdDO2ut3YA:10 a=rl5im9kqc5Lf4LNbBjHf:22 X-Proofpoint-GUID: zDnNNlUfKbzHRtxH6G2phMiHBoiIJX-1 X-Proofpoint-ORIG-GUID: zDnNNlUfKbzHRtxH6G2phMiHBoiIJX-1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-15_01,2026-06-12_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 spamscore=0 bulkscore=0 suspectscore=0 impostorscore=0 clxscore=1015 priorityscore=1501 phishscore=0 adultscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606040000 definitions=main-2606150056 On 5/26/2026 5:52 PM, Stephan Gerhold wrote: > On Tue, May 26, 2026 at 04:24:41PM +0530, Maulik Shah wrote: [...] >> static const struct pdc_cfg pdc_cfg_v3_2 = { >> + .gpio_irq_sts = GENMASK(5, 5), >> + .gpio_irq_mask = GENMASK(4, 4), > > BIT(5) / BIT(4) would be clearer here in my opinion. GENMASK gives uniformity. > >> .irq_enable = GENMASK(3, 3), >> .irq_type = GENMASK(2, 0), >> }; >> [...] >> @@ -184,6 +204,14 @@ static u32 pdc_reg_read(int reg, u32 i) >> return readl_relaxed(pdc->base + reg + i * sizeof(u32)); >> } >> >> +static inline bool pdc_pin_uses_seconary_mode(int pin_out) >> +{ >> + if (pdc->mode == PDC_SECONDARY_MODE && pin_out >= pdc->num_spis) >> + return true; >> + >> + return false; > > Can put this in one line: > > return pdc->mode == PDC_SECONDARY_MODE && pin_out >= pdc->num_spis; > >> +} Sure. >> + [...] >> + >> +static void pdc_clear_gpio_cfg(int pin_out) >> +{ >> + unsigned long gpio_sts; >> + >> + if (pdc->version < PDC_VERSION_3_0) >> + return; >> + >> + gpio_sts = pdc_reg_read(pdc->regs->irq_cfg_reg, pin_out); >> + gpio_sts &= ~pdc->cfg->gpio_irq_sts; >> + pdc_reg_write(pdc->regs->irq_cfg_reg, pin_out, gpio_sts); > > Is this guaranteed to be called sequentially, i.e. not in parallel on > another CPU? Otherwise, you need to add the lock here to make sure the > read-modify-write doesn't race with another CPU. Right. with irq_desc->lock held it will be called sequentially and no locking needed. > > Note that since the irq_cfg_reg is also used in qcom_pdc_gic_set_type() > it would be safest to add the lock there as well (although since PDC has > IRQCHIP_SET_TYPE_MASKED it's probably unlikely to be called in parallel > with another irqchip operation for the same IRQ). In my patch, I handled > this for all users using a new pdc_update_irq_cfg() function [1]. > > [1]: https://github.com/stephan-gh/linux/commit/59ca2a7335ede83e4a7cf02704dd7c469c725c14 > >> +} [...] >> +static void qcom_pdc_ack(struct irq_data *d) >> +{ >> + if (pdc_pin_uses_seconary_mode(d->hwirq) && !irqd_is_level_type(d)) >> + pdc->clear_gpio(d->hwirq); >> +} > > You might need a write memory barrier here and/or read-back here to make > sure the write is complete before the interrupt is unmasked in the GIC. > IIRC I added this in my patch after seeing some test tlmm-test failure.. I did not see any need for barries and all tlmm-test passed. [...] >> >> + pdc->unmask_gpio = pdc_unmask_gpio_cfg; >> + pdc->clear_gpio = pdc_clear_gpio_cfg; > > What is the purpose of these function pointers if you always assign the > same function? I have updated them in v3 to be assigned only for secondary mode. Thanks, Maulik