From: Brian Gerst <bgerst@didntduck.org>
To: davej@suse.de
Cc: "H. Peter Anvin" <hpa@transmeta.com>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>
Subject: Re: [Fwd: CPU detection revamp (Request for comments)]
Date: Fri, 10 Nov 2000 15:33:54 -0500 [thread overview]
Message-ID: <3A0C5BB2.3C48C251@didntduck.org> (raw)
In-Reply-To: <Pine.LNX.4.21.0011101937510.552-100000@neo.local>
davej@suse.de wrote:
>
> On Fri, 10 Nov 2000, Brian Gerst wrote:
>
> > > features : fpu vme de pse tsc msr mce cx8 pge mmx syscall 3dnow
> >
> > The K6's don't support sysenter/sysexit.
>
> The K6 datasheets suggests otherwise.
> Some models seem to have sysenter/sysexit, whilst others have
> syscall/sysret. No model seems to have both.
>
> The datasheets are somewhat confusing, as it doesn't mention bit 10
> at all, just an oversized box for bit 11.
The Athlons support sysenter and syscall, but the K6's only support
syscall. The earlier version of syscall (bit 10) is undocumented by
AMD.
--
Brian Gerst
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next prev parent reply other threads:[~2000-11-10 20:36 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <3A0B6B43.D1210AAA@transmeta.com>
2000-11-10 17:56 ` [Fwd: CPU detection revamp (Request for comments)] davej
2000-11-10 18:20 ` H. Peter Anvin
2000-11-10 19:51 ` davej
2000-11-10 18:50 ` Brian Gerst
2000-11-10 19:49 ` davej
2000-11-10 19:55 ` H. Peter Anvin
2000-11-10 20:26 ` davej
2000-11-10 20:33 ` Brian Gerst [this message]
2000-11-10 23:06 ` davej
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