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From: Jeffrey.Rose@t-online.de (Jeffrey Rose)
To: Erik Mouw <J.A.K.Mouw@ITS.TUDelft.NL>
Cc: Linus Torvalds <torvalds@transmeta.com>,
	Michael Chen <michaelc@turbolinux.com.cn>,
	alan@lxorguk.ukuu.org.uk, linux-kernel@vger.kernel.org
Subject: Re: About Celeron processor memory barrier problem
Date: Sun, 24 Dec 2000 10:45:14 +0100	[thread overview]
Message-ID: <3A45C5AA.D0A5FDF3@t-online.de> (raw)
In-Reply-To: <4015029078.19991223172443@turbolinux.com.cn> <Pine.LNX.4.10.10012230920330.2066-100000@penguin.transmeta.com> <20001224002732.O25239@arthur.ubicom.tudelft.nl>

Erik Mouw wrote:
> 
> On Sat, Dec 23, 2000 at 09:21:51AM -0800, Linus Torvalds wrote:
> > A Celeron isn't a PIII, and you shouldn't tell the configure that it is.
> 
> Well, some Celerons are. My laptop has a Celeron with a Coppermine
> core, so it is PIII based. Here is the output from /proc/cpuinfo:
> 
> processor       : 0
> vendor_id       : GenuineIntel
> cpu family      : 6
> model           : 8
> model name      : Celeron (Coppermine)
> stepping        : 1
> cpu MHz         : 501.140
> cache size      : 128 KB
> fdiv_bug        : no
> hlt_bug         : no
> f00f_bug        : no
> coma_bug        : no
> fpu             : yes
> fpu_exception   : yes
> cpuid level     : 2
> wp              : yes
> flags           : fpu vme de pse tsc msr pae mce cx8 sep mtrr pge mca cmov pat pse36 mmx fxsr sse
> bogomips        : 999.42

I also have a Celeron 600 in my Compaq 5000, but even with the output
below, I am not sure this is what Linus is talking about! I believe
Linus is trying to say, "We HAVE configurations set for that specific
architecture, so please USE them." However, I suppose you are saying you
will get better performance from selecting PIII due to this output? Let
me know ...

jrose$ cat /proc/info 

processor	: 0
vendor_id	: GenuineIntel
cpu family	: 6
model		: 8
model name	: Celeron (Coppermine)
stepping	: 3
cpu MHz		: 598.064
cache size	: 128 KB
fdiv_bug	: no
hlt_bug		: no
f00f_bug	: no
coma_bug	: no
fpu		: yes
fpu_exception	: yes
cpuid level	: 2
wp		: yes
flags		: fpu vme de pse tsc msr pae mce cx8 sep mtrr pge mca cmov pat
pse36 mmx fxsr sse
bogomips	: 1192.76

Cheers,

Jeff
-- 
<Jeffrey.Rose@t-online.de>
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  reply	other threads:[~2000-12-24 10:16 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
1999-12-23  9:24 About Celeron processor memory barrier problem michael chen
2000-12-23 11:04 ` Erik Mouw
2000-12-23 17:21 ` Linus Torvalds
2000-12-23 23:27   ` Erik Mouw
2000-12-24  9:45     ` Jeffrey Rose [this message]
2000-12-24 11:48       ` Erik Mouw
2000-12-23 23:36   ` Matthias Schniedermeyer
2000-12-24  9:36   ` Kai Henningsen
2000-12-24 20:50     ` Tim Wright
2000-12-24 22:25       ` Linus Torvalds
2000-12-25  2:38         ` Tim Wright
2000-12-25  7:19         ` The Doctor What
2000-12-26  1:40         ` Alan Cox
2000-12-26 18:14           ` Linus Torvalds
2000-12-26 22:31             ` Rogier Wolff
2001-01-01 11:55         ` Riley Williams
2000-12-25 11:12       ` Kai Henningsen
2000-12-25 19:37         ` Ian Stirling
2000-12-26 20:38         ` Pavel Machek
2000-12-26  0:15       ` Albert D. Cahalan
2000-12-23 22:34 ` Pavel Machek
     [not found] <fa.gm0b5nv.1h2mope@ifi.uio.no>
     [not found] ` <fa.n7l96dv.2nah0l@ifi.uio.no>
2000-12-26 19:24   ` Giacomo Catenazzi

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