x86 PAT errata

x86 PAT errata

[Mikael Pettersson]

Before people get too exited about the x86 Page Attribute Table ...
Does Linux use mode B (CR4.PSE=1) or mode C (CR4.PAE=1) paging?
If so, known P6 errata must be taken into account.
In particular, Pentium III errata E27 and Pentium II errata A56
imply that only the low four PAT entries are working for 4KB
pages, if CR4.PSE or CR4.PAE is enabled.

/Mikael
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Re: x86 PAT errata

[Jeff Hartmann]

Mikael Pettersson wrote:

> Before people get too exited about the x86 Page Attribute Table ...
> Does Linux use mode B (CR4.PSE=1) or mode C (CR4.PAE=1) paging?
> If so, known P6 errata must be taken into account.
> In particular, Pentium III errata E27 and Pentium II errata A56
> imply that only the low four PAT entries are working for 4KB
> pages, if CR4.PSE or CR4.PAE is enabled.
> 
> /Mikael
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> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
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Yes it does use PSE/PAE paging.  Could you point me to these errata 
documents?  According to the documentation I've seen it says that only 
the low four PAT entries work for 4MB pages.  I've never seen 
documentation that says the same is true for 4k pages.

-Jeff

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Re: x86 PAT errata

[Mikael Pettersson]

Jeff Hartmann wrote:
> > Before people get too exited about the x86 Page Attribute Table ...
> > Does Linux use mode B (CR4.PSE=1) or mode C (CR4.PAE=1) paging?
> > If so, known P6 errata must be taken into account.
> > In particular, Pentium III errata E27 and Pentium II errata A56
> > imply that only the low four PAT entries are working for 4KB
> > pages, if CR4.PSE or CR4.PAE is enabled.
> ...
> Yes it does use PSE/PAE paging.  Could you point me to these errata 
> documents?  According to the documentation I've seen it says that only 
> the low four PAT entries work for 4MB pages.  I've never seen 
> documentation that says the same is true for 4k pages.

They're called "Specification Updates" and are available at
developer.intel.com in the same place you get the manuals
and other docs. The Pentium III one is at
http://developer.intel.com/design/PentiumIII/specupdt/.
According to the errata, one bit which should be used for selecting
PAT entry is forced to zero for 4KB pages, which limits them
to the low four PAT entries. Large pages get to use all entries.

/Mikael
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Re: x86 PAT errata

[H. Peter Anvin]

Followup to:  <200101251745.SAA07063@harpo.it.uu.se>
By author:    Mikael Pettersson <mikpe@csd.uu.se>
In newsgroup: linux.dev.kernel
>
> Before people get too exited about the x86 Page Attribute Table ...
> Does Linux use mode B (CR4.PSE=1) or mode C (CR4.PAE=1) paging?
> If so, known P6 errata must be taken into account.
> In particular, Pentium III errata E27 and Pentium II errata A56
> imply that only the low four PAT entries are working for 4KB
> pages, if CR4.PSE or CR4.PAE is enabled.
> 

All of the above.  Sounds like PAT should be declared broken on these
chips.

	-hpa
-- 
<hpa@transmeta.com> at work, <hpa@zytor.com> in private!
"Unix gives you enough rope to shoot yourself in the foot."
http://www.zytor.com/~hpa/puzzle.txt
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Re: x86 PAT errata

[Jeff Hartmann]

H. Peter Anvin wrote:

> Followup to:  <200101251745.SAA07063@harpo.it.uu.se>
> By author:    Mikael Pettersson <mikpe@csd.uu.se>
> In newsgroup: linux.dev.kernel
> 
>> Before people get too exited about the x86 Page Attribute Table ...
>> Does Linux use mode B (CR4.PSE=1) or mode C (CR4.PAE=1) paging?
>> If so, known P6 errata must be taken into account.
>> In particular, Pentium III errata E27 and Pentium II errata A56
>> imply that only the low four PAT entries are working for 4KB
>> pages, if CR4.PSE or CR4.PAE is enabled.
>> 
> 
> 
> All of the above.  Sounds like PAT should be declared broken on these
> chips.
> 
> 	-hpa

We can do set PAT entry one to be write combined.  Currently it doesn't 
look like anyone is using write through page mapping anywhere in the 
kernel (Just PAGE_PWT set).  Am I correct in that assumption?

-Jeff

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